MAX17558 Datasheet, PDF (23/28 Pages) Maxim Integrated Products – Enhances Power Efficiency

MAX17558
60V, Dual-Output, Synchronous
Step-Down Controller
V_MIL- V_GS on HSMOSFET gate that produces I_DS =
I_LOAD(MAX)
Q_rr is the reverse-recovery charge of low-side MOSFET
body diode (if external Schottky is not placed across low-
side MOSFET),
C_OSSHS is the effective output capacitance of the high-side
MOSFET,
C_OSSLS is the effective output capacitance of the low-side
MOSFET.
Low-side MOSFET losses can be approximated using the
following formula:
P_HSMOSFET = I_LOAD(MAX)2 × R_{DS ON} × 1− D
+ V_D x I_LOAD(MAX) x t_DT x f_SW
where V_D is the forward-drop of the LSMOSFET body
diode and t_DT is the dead time from the Electrical
Characteristics table.
Take the R_DS(ON) variation with temperature into account
while calculating the above losses and ensure that the
losses of each MOSFET do not exceed their power rat-
ing. Using a low Q_rr Schottky diode across the low-side
MOSFET reduces the high-side MOSFET losses.
Power Dissipation within the MAX17558
Gate-charge losses are dissipated by the drivers.
Therefore, the gate-driver current taken from the internal
LDO regulator and resulting power dissipation must be
checked. If V_CCEXT is not used to power V_CCINT, calculate
the approximate IC losses as follows:
P_MAX17558 =V_IN × (Q _Gate × f_SW ) + I_IN
If V_CCEXT is used to power the V_CCINT, use the following
equation to calculate the approximate IC losses:
P_MAX1755=₈ V_CCEXT × (Q _Gate × f_SW ) + I_IN
where:
Q_{Gate =} Total gate charge of high-side and low-side
MOSFETs of controller1 + total gate charge of high-side
and low-side MOSFETs of controller 2,
I_IN is the supply current given in the Electrical
Characteristics table.
Calculate the IC junction temperature using the following
equation and ensure that this value does not exceed
+125°C:
= T_J P_MAX17558 × Rth_JA + T_A
where:
T_J is the IC junction temperature,
P_MAX17558 is the power losses in the IC,
Rth_JA is the IC junction-to-ambient thermal resistance,
which is typically 29°C/W for a multilayer board,
T_A is the maximum ambient temperature.
PCB Layout Guidelines
Careful PCB layout is critical to achieve low losses, low
output noise, and clean and stable operation. Use the
following guidelines for PCB layout:
●● Keep input bypass capacitors as close as possible
across the drain of the high-side MOSFET and source
of the low-side MOSFET.
●● If external Schottky diodes are used across the low-
side MOSFET, keep the Schottky very close and right
across the low-side MOSFET.
●● Keep IN, V_CCINT, V_CCEXT bypass capacitors and
BST_ capacitors nearer to IC pins.
●● Route high-speed switching nodes (BST_, LX_, DH_,
and DL_) away from the sensitive analog areas (RT,
COMP_, CS_, and FB_).
●● The gate current traces must be short and wide. Use
multiple small vias to route these signals if routed from
one layer of the PCB to another layer.
●● Route current-sense lines parallel, short, and next to
each other to minimize the loop formed by these lines.
●● Keep current-sense filter capacitors nearer to IC
current-sense pins and on the same side of the IC.
●● Group all GND-referred and feedback components
close to the IC.
●● Keep the FB_ and compensation-network nets as
small as possible to prevent noise pickup.
●● If possible, place all power components on the top
side of the board and run the power-stage currents
using traces or copper fills on the top side only, without
adding vias.
●● Keep the power traces and load connections short.
This practice is essential for high efficiency. Use thick
copper PCBs (2oz or higher) to enhance efficiency
and minimize trace inductance and resistance.
●● On the top side, lay out a large PGND copper area
for the output and connect the bottom terminals of the
input bypass capacitors, output capacitors, and the
source terminals of the low-side MOSFET to that area.
●● Refer to the MAX17558 evaluation kit data sheet PCB
layout for an example.
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