DS3141 Datasheet, PDF (22/88 Pages) Maxim Integrated Products – Single/Dual/Triple/Quad DS3/E3 Framers

DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers
7.6 Common and Line Interface Registers
This section describes the registers responsible for top-level configuration, control, and status of each framer,
including resets, clocks, pin controls, and line interface functions.
Table 7-C. Common Line Interface Register Map
ADDR
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
00h
ID
ID7
ID6
ID5
ID4
01h
MC1
LOTCMC
ZCSD
BIN
MECU
02h
MC2
OSTCS
TCCLK
N/A
N/A
03h
MC3
TDENMS
TSOFC
TOHENI
TOHI
04h
MC4
RDENMS
ROOFI
RLOSI
RDATH
05h
MC5
RNEGI
RPOSI
RCLKI
TNEGH
06h
ISR1
N/A
N/A
N/A
N/A
08h
MSR
LORC
LOTC
T3E3
FEAC
09h
MSRL
LORCL
LOTCL
N/A
N/A
0Ah
MSRIE
LORCIE
LOTCIE
T3E3IE
FEACIE
BIT 3
ID3
AECU
N/A
TSOFI
RSOFI
TPOSH
INT4
HDLC
N/A
HDLCIE
BIT 2
ID2
TUA1
DLB
TICLKI
ROCLKI
TNEGI
INT3
BERT
N/A
BERTIE
BIT 1
ID1
DISABLE
LLB
TDATI
RDATI
TPOSI
INT2
COVF
COVFL
COVFIE
BIT 0
ID0
RST
PLB
TDENI
RDENI
TCLKI
INT1
N/A
OSTL
OSTIE
Register Name:
Register Description:
Register Address:
ID
ID Register
00h
Bit #
7
6
5
4
3
Name
ID7
ID6
ID5
ID4
ID3
Default
—
—
—
—
—
2
1
0
ID2
ID1
ID0
—
—
—
This register is a global resource and is mapped into address 00h in every framer in the device.
Bits 0 to 7: Device ID (ID[7:0]). Read-only. Contact the factory for details on the meaning of the ID bits.
Register Name:
Register Description:
Register Address:
MC1
Master Configuration Register 1
01h
Bit #
7
6
5
4
3
2
1
0
Name
LOTCMC ZCSD
BIN
MECU
AECU
TUA1
DISABLE
RST
Default
0
0
0
0
0
1
0
0
Bit 0: Framer Reset (RST). When this bit is set to logic 1, it forces all the internal registers in the framer (except
this RST bit) to their default state. Only the framer associated with this register is reset. RST must be high for a
minimum of 100ns and then returned low. This register bit is logically ORed with the RST pin.
0 = normal operation
1 = force all internal registers to their default values
Bit 1: Framer Disable (DISABLE). Setting this bit disables the framer by stopping all clocks. This reduces the
power the framer requires. After the framer is enabled again by clearing this bit, the RST bit must be toggled to
initialize the framer again. Toggling the RST bit when DISABLE = 1 automatically enables the framer again.
0 = enable framer
1 = disable framer
Bit 2: Transmit Unframed All Ones (TUA1). Enables the transmission of an unframed all-ones pattern on
TPOS/TNEG or TNRZ. This pattern is sometimes called physical AIS.
0 = disable transmission of unframed all ones
1 = enable transmission of unframed all ones (reset default value)
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