MAX1718T_08 Datasheet, PDF (21/34 Pages) Maxim Integrated Products – Notebook CPU Step-Down Controller

Notebook CPU Step-Down Controller
2.7V TO 5.5V
1kΩ
100kΩ
1kΩ
100kΩ
D4
MAX1718T
D3
D2
D1
D0
ZMODE
1kΩ
ZMODE = HIGH = 1.25V
ZMODE = LOW = 1.15V
NOTE: USE PULLUP FOR LOGIC MODE 1, PULL-DOWN FOR LOGIC MODE 0.
USE ≥100kΩ FOR IMPEDANCE MODE 1, ≤1kΩ FOR IMPEDANCE MODE 0.
Figure 12. Using the Internal Mux with Both VID Codes Resistor Programmed
eral processor types can be used without hardware
modifications. Figure 14 shows one way to implement
this function. The desired code is determined by the
system BIOS and programmed into one register of the
MAX1609 using the SMBus™ serial interface. The
MAX1609’s other register is left in its power-up state (all
outputs high impedance). When SMBSUS is low, the
outputs are high impedance and do not affect the logic-
mode VID code setting. When SMBSUS is high, the pro-
grammed register is selected, and the MAX1609 forces
a low impedance on the appropriate VID input pins. The
ZMODE signal is delayed relative to the SMBSUS pin
because the VID pins that are pulled low by the
MAX1609 take significant time to rise when they are
released. One additional benefit of using the MAX1609
for this application is that the application uses only five
of the MAX1609’s high-voltage, open-drain outputs. The
other three outputs can be used for other purposes.
Output Voltage Transition Timing
The MAX1718T is designed to perform output voltage
transitions in a controlled manner, automatically mini-
mizing input surge currents. This feature allows the cir-
cuit designer to achieve nearly ideal transitions,
guaranteeing just-in-time arrival at the new output volt-
Table 5. DAC Mux Operation
ZMODE
GND
V_CC
X
SUS
GND
GND
V_CC
OUTPUT VOLTAGE
DETERMINED BY
Logic level of D0–D4
Impedance of D0–D4
Logic levels of S0, S1
age level with the lowest possible peak currents for a
given output capacitance. This makes the IC ideal for
mobile CPUs.
Mobile CPUs operate at multiple clock frequencies,
which often require distinct VID settings. When transi-
tioning from one clock frequency to the other, the CPU
first goes into a low-power state, then the output volt-
age and clock frequency are changed. The change
must be accomplished in a specified transition time or
the system can halt.
At the beginning of an output voltage transition, the
MAX1718T blanks the VGATE output, preventing it from
going low. VGATE remains blanked during the transition
and is reenabled when the slew-rate controller has set
the internal DAC to the final value and one additional
SMBus is a trademark of Intel Corp.
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