MAX1127 Datasheet, PDF (21/25 Pages) Maxim Integrated Products – Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs

Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs
1 LSB =2 ^{x FSR}
4096
FSR
0x7FF
0x7FE
0x7FD
FSR = 700mV xVREFIO
1.24V
FSR
1 LSB =2 ^{x FSR}
4096
FSR
0xFFF
0xFFE
0xFFD
FSR = 700mV xVREFIO
1.24V
FSR
0x001
0x000
0xFFF
0x801
0x800
0x7FF
0x803
0x802
0x801
0x800
-2047 -2045
-1 0 +1
+2045 +2047
DIFFERENTIAL INPUT VOLTAGE (LSB)
Figure 6. Bipolar Transfer Function with Two’s Complement
Output Code (T/B = 0)
Double Termination (DT)
As shown in Figure 8, the MAX1127 offers an optional,
internal 100Ω termination between the differential output
pairs (OUT_P and OUT_N, CLKOUTP and CLKOUTN,
FRAMEP and FRAMEN). In addition to the termination
at the end of the line, a second termination directly at
the outputs helps eliminate unwanted reflections down
the line. This feature is useful in applications where
trace lengths are long (>5in) or with mismatched
impedance. Drive DT high to select double termination,
or drive DT low to disconnect the internal termination
resistor (single termination). Selecting double termina-
tion increases the OV_DD supply current (see the
Electrical Characteristics table).
Power-Down Modes
The MAX1127 offers two types of power-down inputs,
PD0–PD3 and PDALL. The power-down modes allow
the MAX1127 to use power efficiently by transitioning to
a low-power state when conversions are not required.
Independent Channel Power-Down (PD0–PD3)
PD0–PD3 control the power-down mode of each chan-
nel independently. Drive a power-down input high to
power down its corresponding input channel. For exam-
ple, to power down channel 1, drive PD1 high. Drive a
power-down input low to place the corresponding input
channel in normal operation. The differential output
impedance of a powered-down output channel is
approximately 378Ω, when DT is low. The output imped-
ance of OUT_P, with respect to OUT_N, is 100Ω when
0x003
0x002
0x800
0x000
-2047 -2045
-1 0 +1
+2045 +2047
DIFFERENTIAL INPUT VOLTAGE (LSB)
Figure 7. Bipolar Transfer Function with Offset Binary Output
Code (T/B = 1)
DT
OUT_P/
CLKOUTP/
FRAMEP
Z₀ = 50Ω
100Ω
100Ω
MAX1127
OUT_N/
CLKOUTN/
FRAMEN
Z₀ = 50Ω
SWITCHES ARE CLOSED WHEN DT IS HIGH.
SWITCHES ARE OPEN WHEN DT IS LOW.
Figure 8. Double Termination
DT is high. See the Electrical Characteristics table for
typical supply currents with powered-down channels.
The state of the internal reference is independent of the
PD0–PD3 inputs. To power down the internal reference
circuitry, drive PDALL high (see the Global Power-
Down (PDALL) section).
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