MAX9242_09 Datasheet, PDF (20/23 Pages) Maxim Integrated Products – 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance

21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
trace used (microstrip or stripline). Note that two 50Ω
PC board traces do not have 100Ω differential imped-
ance when brought close together—the impedance
goes down when the traces are brought closer.
Route the PC board traces for an LVDS channel (there
are two conductors per LVDS channel) in parallel to
maintain the differential characteristic impedance.
Place the termination resistor at the end of the PC
board traces within a 1/4 inch of the LVDS receiver
input. Avoid vias. If vias must be used, use only one
pair per LVDS channel and place the via for each line
at the same point along the length of the PC board
traces. This way, any reflections will occur at the same
time. Do not make vias into test points for ATE. Make
LVDS clock and data pairs the same length on the PC
board to avoid pair-to-pair skew. Make the PC board
traces that make up a differential pair the same length
to avoid skew within the differential pair.
5V-Tolerant Input
PWRDWN is 5V tolerant and is internally pulled down to
GND. SSG and DCB are not 5V tolerant. The input voltage
range for SSG and DCB is nominally ground to V_CC.
Skew Margin (RSKM)
Skew margin (RSKM) is the time allowed for degrada-
tion of the serial-data sampling setup and hold times by
sources other than the deserializer. The deserializer
sampling uncertainty is accounted for and does not
need to be subtracted from RSKM. The main outside
contributors of jitter and skew that subtract from RSKM
are interconnect intersymbol interference, serializer
pulse position uncertainty, and pair-to-pair path skew.
V_CCO Output Supply and Power Dissipation
The outputs have a separate supply (V_CCO) for interfacing
to systems with 1.8V to 5V nominal input logic levels. The
DC Electrical Characteristics table gives the maximum
supply current for V_CCO = 3.6V with 8pF load at several
switching frequencies with all outputs switching in the
worst-case switching pattern. The approximate incremen-
tal supply current for V_CCO other than 3.6V with the same
8pF load and worst-case pattern can be calculated using:
I_I = C_TV_I 0.5f_C x 21 (data outputs)
+ C_TV_If_C x 1 (clock output)
where:
I_I = incremental supply current
C_T = total internal (C_INT) and external (C_L) load capaci-
tance
V_I = incremental supply voltage
f_C = output clock switching frequency
The incremental current is added to (for V_CCO > 3.6V)
or subtracted from (for V_CCO < 3.6V) the DC Electrical
Characteristics table maximum supply current. The
internal output buffer capacitance is C_INT = 6pF. The
worst-case pattern switching frequency of the data out-
puts is half the switching frequency of the output clock.
In the following example, the incremental supply current
of the MAX9244 in spread and DC-balanced mode is cal-
culated for V_CCO = 5.5V, f_C = 34MHz, and C_L = 8pF:
V_I = 5.5V - 3.6V = 1.9V
C_T = C_INT + C_L = 6pF + 8pF = 14pF
where:
I_I = C_TV_I 0.5f_C x 21 (data outputs) + C_TV_If_C x 1 (clock
output)
I_I = (14pF x 1.9V x 0.5 x 34MHz x 21) + (14pF x 1.9V x
34MHz)
I_I = 9.5mA + 0.9mA = 10.4mA.
The maximum supply current in DC-balanced mode for
V_CC = V_CCO = 3.6V at f_C = 34MHz is 125mA (from the
DC Electrical Characteristics table). Add 10.4mA to get
the total approximate maximum supply current at V_CCO
= 5.5V and V_CC = 3.6V.
If the output supply voltage is less than V_CCO = 3.6V,
the reduced supply current can be calculated using the
same formula and method.
At high switching frequency, high supply voltage, and
high capacitive loading, power dissipation can exceed
the package power dissipation rating. Do not exceed
the maximum package power dissipation rating. See
the Absolute Maximum Ratings for maximum package
power dissipation capacity and temperature derating.
Rising- or Falling-Edge Output Strobe
The MAX9242 has a rising-edge output strobe, which
latches the parallel output data into the next chip on the
rising edge of RxCLKOUT. The MAX9244/MAX9246/
MAX9254 have a falling-edge output strobe, which
latches the parallel output data into the next chip on the
falling edge of RxCLKOUT_. The deserializer output
strobe polarity does not need to match the serializer
input strobe polarity.
Three-Level Logic Inputs
SSG and DCB (DCB mid level is reserved) are three-
level-logic inputs. A logic-high input voltage must be
greater than +2.5V and a logic-low input voltage must
be less than +0.8V. A mid-level logic is recognized by
the MAX9242/MAX9244/MAX9246/MAX9254 when the
input is left open or connected to a driver in a high-
impedance state. A weak inverter on the input stage of
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