MAX1964 Datasheet, PDF (20/30 Pages) Maxim Integrated Products – Tracking/Sequencing Triple/Quintuple Power-Supply Controllers

Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
I_PEAK
=
V_OUTV_REFA_VEA
V_OUT(NOMINAL)R_DS(ON)A_VCS
where V_REF = 1.24V, A_VCS is the current-sense amplifi-
er’s gain (4.9 typ), A_VEA is the DC gain of the transcon-
ductance error amplifier (2000 typ) set by its DC output
resistance, and V_OUT(NOMINAL) is the output voltage
set by the feedback resistive-divider (internal or exter-
nal). Since the output voltage is a function of the load
current and load resistance, the total DC loop gain
(A_V(DC)) is approximately:
A_V(DC)
≈
I_PEAK
I_LOAD
≈
V_REFR_LOADA_VEA
V_OUT(NOMINAL)R_DS(ON)A_VCS
≈ ^{400 × VREFRLOAD}
V_OUT(NOMINAL)R_DS(ON)
The first compensation capacitor (C_COMP1) creates the
dominant pole. Due to the current-mode control
scheme, the output capacitor also creates a pole in the
system which is a function of the load resistance. As
the load resistance increases, the frequency of the out-
put capacitor’s pole decreases. However, the DC loop
gain increases with larger load resistance, so the unity-
gain bandwidth remains fixed. Additionally, the com-
pensation resistor and the output capacitor’s ESR both
generate zeros which must be canceled out by corre-
sponding poles. Therefore, in order to achieve stable
operation, use the following procedure to properly com-
pensate the system:
1) The crossover frequency (the frequency at which
unity gain occurs) must be less than 1/5th the
switching frequency:
f_C
≤
f_SW
5
2) Determine the series compensation capacitor
(C_COMP1) required to set the desired crossover fre-
quency:
C_COMP1
≥
1
2π


g_m A_V(DC)
2000f_C


where the error amplifier’s transconductance (g_m)
is 100µS (see Electrical Characteristics) and A_V(DC)
is the total DC loop gain defined above.
3) Before crossover occurs, the output capacitor and
the load resistor generate a second pole:
f_POLE(OUT)
=
1
2πC_OUTR_LOAD
=
I_LOAD(MAX)
2πC_OUTV_OUT
4) The series compensation resistor and capacitor
provide a zero which can be used to cancel the
second pole in order to ensure stability:
R_COMP
≥
1
2πC_COMP1f_POLE(OUT)
5) For most applications using electrolytic capacitors,
the output capacitor’s ESR forms a second zero
that occurs before crossover. Applications using
low-ESR capacitors (e.g., polymer, OS-CON) may
have ESR zeros that occur after crossover.
Therefore, verify the frequency of the output capaci-
tor’s ESR zero:
f_ZERO(ESR)
≈
1
2πC_OUTR_ESR
6) Finally, if the output capacitor’s ESR zero occurs
before crossover, add the parallel compensation
capacitor (C_COMP2) to form a third pole to cancel
this second zero:
( ) ^{CCOMP2 ≈}
C_COMP1
2πR_COMPC_COMP1f_ZERO(ESR) - 1
( ) ≈ CCOMP1fPOLE(OUT)
f_ZERO(ESR) - f_POLE(OUT)
For example, the MAX1964 Standard Application
Circuit shown in Figure 1 requires a 5V output that sup-
ports up to 2A. Using the above compensation guide-
lines, we can determine the proper component values:
• First, select the crossover frequency to be 1/5th the
200kHz switching frequency.
• Next, determine the total DC loop gain (A_V(DC)) so
you can calculate the series compensation capaci-
tance (C_COMP1). Since the applications circuit uses
the International Rectifier IRF7101 with an R_DS(ON)
of 100mΩ, the DC loop gain approximately equals
2480 and C_COMP1 must be approximately 490pF.
Select the closest standard capacitor value of
470pF.
• Determine the location of the output pole
(f_POLE(OUT)). With a 5V output supplying 2A and a
1000µF electrolytic capacitor, the output pole
occurs at 64Hz.
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