MAX17000_13 Datasheet, PDF (20/32 Pages) Maxim Integrated Products – Complete DDR2 and DDR3 Memory Power-Management Solution

MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
Valley Current-Limit Protection
The MAX17000 uses the same valley current-limit pro-
tection employed on all Maxim Quick-PWM controllers. If
the current exceeds the valley current-limit threshold,
the PWM controller is not allowed to initiate a new cycle.
The actual peak current is greater than the valley cur-
rent-limit threshold by an amount equal to the inductor
ripple current. Therefore, the exact current-limit charac-
teristic and maximum load capability are a function of
the inductor value and battery voltage. When combined
with the undervoltage-protection circuit, this current-limit
method is effective in almost every circumstance.
In forced-PWM mode, the MAX17000 also implements
a negative current limit to prevent excessive reverse
inductor currents when V_OUT is sinking current. The
negative current-limit threshold is set to approximately
115% of the positive current limit. See Figure 5.
I_PEAK
I_LOAD
( ) ^ILIM(VAL)
= I_LOAD(MAX)
1-
LIR
2
I_LIMIT
0
TIME
Figure 5. Valley Current-Limit Threshold Point
Power-Good Outputs
(PGOOD1 and PGOOD2)
The MAX17000 features two power-good outputs.
PGOOD1 is the open-drain output for a window com-
parator that continuously monitors the SMPS output.
PGOOD1 is actively held low in shutdown and during
soft-start and soft-shutdown. After the soft-start termi-
nates, PGOOD1 becomes high impedance as long as
the SMPS output voltage is between 115% (typ) and
85% (typ) of the regulation voltage. When the SMPS
output voltage exceeds the 115%/85% regulation win-
dow, the MAX17000 pulls PGOOD1 low. Any fault con-
dition on the SMPS output forces PGOOD1 and
PGOOD2 low and latches off until the fault latch is
cleared by toggling SHDN or cycling V_CC power below
1V. Detection of an OVP event immediately pulls
PGOOD1 low, regardless of the OVP state (OVP
enabled or disabled).
20
PGOOD2 is the open-drain output for a window com-
parator that continuously monitors the VTT output.
PGOOD2 is actively held low in standby, shutdown,
and during soft-start. PGOOD2 becomes high imped-
ance as long as the VTT output voltage is within ±10%
of the regulation voltage. When the VTT output exceeds
the ±10% threshold, the MAX17000 pulls PGOOD2 low.
If PGOOD2 remains low for 5ms (typ), the MAX17000
latches off with the soft-shutdown sequence.
For logic-level output voltages, connect an external 100kΩ
pullup resistor from PGOOD1 and PGOOD2 to V_DD.
POR, UVLO
Power-on reset (POR) occurs when V_CC rises above
approximately 2V, resetting the fault latch and soft-start
circuit and preparing the controller for power-up. When
OVP is enabled, a rising edge on POR turns on the 16Ω
discharge MOSFET on CSL and VTT. When OVP is dis-
abled, the internal 16Ω discharge MOSFETs on CSL
and VTT also remain off.
V_CC undervoltage lockout (UVLO) circuitry inhibits
switching until V_CC reaches 4.1V (typ). When V_CC rises
above 4.1V, the controller activates the PWM controller
and initializes soft-start. When V_CC drops below the
UVLO threshold (falling edge), the controller stops, DL
is pulled low, and the internal 16Ω discharge
MOSFETs on the CSL and VTT outputs are enabled, if
OVP is enabled.
Soft-Start and Soft-Shutdown
Soft-start and soft-shutdown for the MAX17000 PWM
block is voltage based. Soft-start begins when SHDN is
driven high. During soft-start, the PWM output is
ramped up from 0V to the final set voltage in 1.4ms.
This reduces inrush current and provides a predictable
ramp-up time for power sequencing. The MAX17000
always uses skip mode during startup, regardless of
the SKIP and STDBY setting. The SKIP and STDBY con-
trols take effect after soft-start is done.
The MAX17000 VTT LDO regulator uses a current-limited
soft-start function. When the VTT block is enabled, the
internal source and sink current limits are linearly
increased from zero to the full-scale limit in 160μs. Full-
scale current limit is available when the VTT output is in
regulation, or after 160μs, whichever is earlier. The VTTR
reference buffer does not have any soft-start control.
Maxim Integrated