MAX104 Datasheet, PDF (20/32 Pages) Maxim Integrated Products – ±5V, 1Gsps, 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier

±5V, 1Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
Table 5. DC-Coupled Clock Drive Options
CLOCK DRIVE
Single-Ended Sine Wave
Differential Sine Wave
Single-Ended ECL
Differential ECL
CLK+
-10dBm to +4dBm
-10dBm to +4dBm
ECL Drive
ECL Drive
CLK-
External 50Ω to GNDI
-10dBm to +4dBm
-1.3V
ECL Drive
CLKCOM
GNDI
GNDI
-2V
-2V
REFERENCE
Figure 13a
Figure 13b
Figure 13c
Figure 13d
inputs are AC-coupled. Under this condition, connect
CLKCOM to GNDI. Single-ended ECL/PECL/sine-wave
drive is also possible if the undriven clock input is
reverse-terminated to GNDI through a 50Ω resistor in
V_CCO
series with a capacitor whose value is identical to that
used to couple the driven input.
Demux Reset Operation
The MAX104 features an internal 1:2 demultiplexer that
reduces the data rate of the output digital data to one-
half the sample clock rate. Demux reset is necessary
when interleaving multiple MAX104s and/or synchroniz-
ing external demultiplexers. The simplified block diagram
of Figure 1 shows that the demux reset signal path con-
sists of four main circuit blocks. From input to output,
they are the reset input dual latch, the reset pipeline, the
demux clock generator, and the reset output. The sig-
nals associated with the demux reset operation and the
control of this section are listed in Table 6.
50k
50k
RSTIN+
RSTIN-
20µA
Reset Input Dual Latch
The reset input dual-latch circuit block accepts differ-
ential PECL reset inputs referenced to the same V_CCO
power supply that powers the MAX104 PECL outputs.
For applications that do not require a synchronizing
reset, the reset inputs can be left open. In this case,
they will self-bias to a proper level with internal 50kΩ
resistors and 20µA current source. This combination
creates a -1V difference between RSTIN+ and RSTIN-
to disable the internal reset circuitry. When driven with
PECL logic levels terminated with 50Ω to (V_CCO - 2V),
the internal biasing network can easily be overdriven.
Figure 14 shows a simplified schematic of the reset
input structure.
To properly latch the reset input data, the setup time
(t_SU) and the data hold time (t_HD) must be met with
respect to the rising edge of the sample clock. The tim-
ing diagram of Figure 15 shows the timing relationship
of the reset input and sampling clock.
RESET INPUTS ARE
ESD PROTECTED
(NOT SHOWN IN THIS
SIMPLIFIED DRAWING).
GNDD
Figure 14. Simplified Reset Input Structure
RSTIN+
50%
50%
RSTIN-
t_SU
t_HD
CLK+
50%
CLK-
Figure 15. Reset Input Timing Definitions
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