DS1875 Datasheet, PDF (20/92 Pages) Maxim Integrated Products – PON Triplexer and SFP Controller

PON Triplexer and SFP Controller
TRIP CONDITION
mCLK
(525kHz)
CAPTURE ALARM
M3QT ALARM
(UNLATCHED)
Figure 4. M3QT Timing
ONE ADC CYCLE
MON4
TEMP
V_CC
Figure 5. ADC Timing with EN5TO8B = 0
MON1 MON2 MON3
MON4
TEMP
t_FRAME1
TEMP
V_CC
MON1 MON2 MON3 MON4
MON5
MON6
TEMP
V_CC
MON1 MON2 MON3 MON4
MON7
MON8
t_FRAME2
t_FRAME2
Figure 6. ADC Timing with EN5TO8B = 1
The ADC results (after right-shifting, if used) are com-
pared to high and low alarm and warning thresholds
after each conversion. The alarm values can be used to
trigger the TX-F or FETG outputs. These ADC thresholds
are user programmable through the I²C interface, as
well as masking registers that can be used to prevent
the alarms from triggering the TX-F and FETG outputs.
Table 3. ADC Default Monitor Ranges
SIGNAL
Temperature (°C)
V_CC (V)
MON1–MON8 (V)
+FS
SIGNAL
127.996
6.5528
2.4997
+FS
HEX
7FFF
FFF8
FFF8
-FS
SIGNAL
-128
0
0
-FS
HEX
8000
0000
0000
ADC Timing
There are 10 analog channels that are digitized in a
sequential fashion. The MON5–MON8 channels are
sampled depending on the state of the EN5TO8B bit in
Table 02h, Register 89h. If the bit is programmed to
logic 0, the ADC cycles through temperature, V_CC, and
MON1–MON4 (Figure 5). If the bit is programmed to
logic 1, all 10 channels are digitized, including chan-
nels MON5–MON8 (Figure 6). In this mode (EN5TO8B
= 0), each of MON5–MON8 is sampled on alternate
cycles, as shown in Figure 5. The total time required to
convert one set of channels is the sequential ADC
cycle time, t_FRAME1 or t_FRAME2 (see Figure 6).
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