MAX3645EEE Datasheet, PDF (2/10 Pages) Maxim Integrated Products – +2.97V to +5.5V, 125Mbps to 200Mbps Limiting Amplifier

+2.97V to +5.5V, 125Mbps to 200Mbps Limiting
Amplifier with Loss-of-Signal Detector
ABSOLUTE MAXIMUM RATINGS
Power-Supply Voltage (V_CCA, V_CCE) ....................-0.5V to +7.0V
Voltage at CAZ1, CAZ2, DIN+,
DIN-, CSD, DIS, TH ................................-0.5V to (V_CC + 0.5V)
PECL Output Current (DOUT+, DOUT-, LOS, LOS) ...........50mA
Differential Voltage between CAZ1 and CAZ2......-1.5V to +1.5V
Differential Voltage between DIN+ and DIN- ........-1.5V to +1.5V
Continuous Power Dissipation (T_A = +85°C)
16-Pin SO (derate 8.7mW/°C above +85°C)................565mW
16-Pin QSOP (derate 8.3mW/°C above +85°C)...........540mW
Storage Ambient Temperature Range (T_S)…….-65°C to +160°C
Lead Temperature (soldering, 10s)...........……………….+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V_CC = +2.97V to +5.5V, PECL outputs are terminated with 50Ω to V_CC - 2V, R_TH = 100Ω, C_AZ = 0.1µF, C_SD = 1nF, T_A = -40°C to
+85°C. Typical values are at V_CC = +3.3V, T_A = +25°C, unless otherwise noted.)
PARAMETER
POWER SUPPLY
Supply Current
INPUT SPECIFICATIONS
Input Resistance
Input Sensitivity (Note 1)
Input Overload (Note 1)
Input-Referred Offset Voltage
Input Common-Mode Voltage
Input-Referred RMS Noise
DIS Input High
DIS Input Low
DIS Input Current
OUTPUT SPECIFICATIONS
PECL Output-Voltage High
PECL Output-Voltage Low
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
I_CC
Excludes PECL termination currents
18
27
mA
R_IN
V_IN-MIN
V_IN-MAX
Single ended; V_IN = ±200mV
Single ended
Differential
Single ended
Differential
Unterminated input, output offset divided by
DC gain (Note 2)
3.3
750
1500
V_CMM
V_IN-NOISE (Notes 2, 3)
V_IH
PECL or CMOS logic
V_CC -
1160
V_IL
PECL or CMOS logic
0
I_IL, I_IH 0V ≤ V_DIS ≤ V_CC
-10
4.8
2
V_CC -
0.87
36
6.4
0.5
1.0
40
50
V_CC
V_CC -
1480
+10
kΩ
mV_P-P
mV_P-P
µV
V
µV_RMS
mV
mV
µA
(Notes 1, 2)
(Notes 1, 2)
V_CC -
1085
V_CC -
1830
V_CC -
880
mV
V_CC -
1555
mV
Data Output Transition Time
Pulse-Width Distortion
t_R, t_F
PWD
20% to 80% (Notes 1, 2, 4)
(Notes 1, 2, 4, 5)
0.7
1.4
ns
30
200
ps
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