MAX14850PMB1 Datasheet, PDF (2/7 Pages) Maxim Integrated Products – MAX14850PMB1 Peripheral Module

MAX14850PMB1 Peripheral Module
DESIGNATION QTY
DESCRIPTION
C1, C2
0.1FF Q10%, 16V X7R ceramic
2 capacitors (0603)
Murata GRM188R71C104KA01D
1FF Q10%, 10V X7R ceramic
C3
1 capacitor (0603)
TDK C1608X7R1A105K
J1
1
12-pin (2 x 6) right-angle male
header
Component List
DESIGNATION QTY
DESCRIPTION
J2
1
12-pin (2 x 6) right-angle female
header
J3
1 2-pin straight male header
R1–R6
6 150I Q5% resistors (0603)
R7–R10
4 4.7kI Q5% resistors (0603)
U1
1
6-channel digital isolator (16 SO)
Maxim MAX14850ASE+
—
1 PCB: EPCB14850PM1
Component Suppliers
SUPPLIER
Murata Electronics North America, Inc.
TDK Corp.
PHONE
770-436-1300
847-803-6100
WEBSITE
www.murata-northamerica.com
www.component.tdk.com
Note: Indicate that you are using the MAX14850PMB1 when contacting these component suppliers.
Detailed Description
UART Interface
The MAX14850PMB1 peripheral module can interface
to the host by plugging directly into a Pmod-compatible
port (configured for SPI or UART) through connector J1.
See Table 1.
Connector J2 provides the galvanically isolated connec-
tion to another peripheral module. Note that even though
the pinout numbering is different than J1, the signals from
the top row of pins on J1 are passed through to the top
row of pins on J2. See Table 2.
Connector J3 provides power from the 2nd power domain
to the isolated side of the IC and the isolated Pmod.
Software and FPGA Code
Example software and drivers are available that execute
directly without modification on several FPGA devel-
opment boards that support an integrated or synthe-
sized microprocessor. These boards include the Digilent
Nexys 3, Avnet LX9, and Avnet ZEDBoard, although
other platforms can be added over time. Maxim provides
complete Xilinx ISE projects containing HDL, Platform
Studio, and SDK projects. In addition, a synthesized bit
stream, ready for FPGA download, is provided for the
demonstration application.
The software project (for the SDK) contains several
source files intended to accelerate customer evalu-
ation and design. These include a base application
(maximModules.c) that demonstrates module functional-
Table 1. Connector J1 (with SPI/UART
Peripheral Attached to J2)
PIN
SIGNAL
DESCRIPTION
1
SS_CTS
Serial select/clear to send
2
MOSI_TXD Master-out slave input/host transmit
3
MISO_RXD Master-in slave output/host receive
4
SCK_RTS Serial clock/ready to send
5
GND
Ground
6
VCC
Power supply
7
SPAREIN Spare input from Pmod to host
8
N.C.
Not connected
9
N.C.
Not connected
10
SPAREIO Spare input/output
11
GND
Ground
12
VCC
Power supply
ity, and uses an API interface (maximDeviceSpecific
Utilities.c) to set and access Maxim device functions
within a specific module.
The source code is written in standard ANSI C format, and
all API documentation including theory/operation, register
description, and function prototypes are documented in
the API interface file (maximDeviceSpecificUtilities.h & .c).
The complete software kit is available for download at
www.maxim-ic.com. Quick start instructions are also
available as a separate document.
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