MAX5813_13 Datasheet, PDF (19/30 Pages) Maxim Integrated Products – Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered

MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I²C Interface
Readback of all other registers is not directly supported.
All requests to read unsupported registers reads back
the device’s reference status and the device ID and revi-
sion information in the format as shown in Table 3.
Interface Verification I²C
Readback Operations
While the MAX5813/MAX5814/MAX5815 support stan-
dard I²C readback of selected registers, it is also
capable of functioning in an interface verification mode.
This mode is accessed any time a readback operation
follows an executed write mode command. In this mode,
the last executed three-byte command is read back in its
entirety. This behavior allows verification of the interface.
Sample command sequences are shown in Figure 7.
The first command transfer is given in write mode with
R/W = 0 and must be run to completion to qualify for
interface verification readback. There is now a STOP/
START pair or Repeated START condition required, fol-
lowed by the readback transfer with R/W = 1 to indicate
a read and an acknowledge clock from the MAX5813/
MAX5814/MAX5815. The master still has control of the
SCL line but the MAX5813/MAX5814/MAX5815 take over
the SDA line. The final three bytes in the frame contain
the command and register data written in the first transfer
presented for readback, followed by a STOP condition. If
additional bytes beyond those required to read back the
requested data are provided, the MAX5813/MAX5814/
MAX5815 will continue to read back ones.
It is not necessary for the write and read mode transfers
to occur immediately in sequence. I²C transfers involv-
ing other devices do not impact the MAX5813/MAX5814/
MAX5815 readback mode. Toggling between readback
modes is based on the length of the preceding write
mode transfer. Combined format I²C readback operation
is resumed if a write command greater than two bytes
but less than four bytes is supplied. For commands writ-
ten using multiple register write sequences, only the last
command executed is read back. For each command
written, the readback sequence can only be completed
one time; partial and/or multiple attempts to readback
executed in succession will not yield usable data.
Table 3. Standard I²C User Readback Data
COMMAND BYTE (REQUEST)
READBACK DATA HIGH BYTE
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8
0000
DAC selection
CODEn[11:4]
0001
DAC selection
DACn[11:4]
0010
DAC selection
DACn[11:4]
0011
DAC selection
DACn[11:4]
0 1 0 0 0 0XX0 0 0 0 0 0 0 0
10000000
CODEA[11:4]
10000001
DACA[11:4]
10100010
DACA[11:4]
10110011
DACA[11:4]
READBACK DATA LOW BYTE
B7 B6 B5 B4 B3 B2 B1 B0
CODEn[3:0]
0000
DACn[3:0]
0000
DACn[3:0]
0000
DACn[3:0]
0000
0 0 0 0 PWD PWC PWB PWA
CODEA[3:0]
0000
DACA[3:0]
0000
DACA[3:0]
0000
DACA[3:0]
0000
Any other command (TSSOP)
Any other command (WLP)
1111 1000
1001 1000
000
REV_ID[2:0] REF MODE
000
(010)
RF[1:0]
Table 4. Format DAC Data Bit Positions
PART
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
MAX5813 D7 D6 D5 D4 D3 D2 D1 D0 x
x
x
x
x
x
x
x
MAX5814 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 x
x
x
x
x
x
MAX5815 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 x
x
x
x
Maxim Integrated
  19