MAX16833 Datasheet, PDF (19/22 Pages) Maxim Integrated Products – High-Voltage HB LED Drivers with Integrated High-Side Current Sense

High-Voltage HB LED Drivers with
Integrated High-Side Current Sense
at fZRHP/5 and C4 is chosen to set the integrator zero
frequency to maintain loop stability. For optimum per-
formance, choose the components using the following
equations:
R10 =
2 × f_ZRHP × R4
F_C × (1 − D_MAX ) × R7 × 6.15 × GM_COMP
The value of C4 can be calculated as below:
C4 =
25
π × R10 × f_ZRHP
where R10 is the compensation resistor in ohms, fZRHP
and fP2 are in hertz, R4 is the inductor current-sense
resistor in ohms, R7 is the LED current-sense resistor in
ohms, factor 6.15 is the gain of the LED current-sense
amplifier, and GMCOMP is the transconductance of the
error amplifier in amps/volts.
Layout Recommendations
Typically, there are two sources of noise emission in a
switching power supply: high di/dt loops and high dV/
dt surfaces. For example, traces that carry the drain cur-
rent often form high di/dt loops. Similarly, the heatsink
of the MOSFET connected to the device drain presents
a dV/dt source; therefore, minimize the surface area of
the heatsink as much as is compatible with the MOSFET
power dissipation or shield it. Keep all PCB traces car-
rying switching currents as short as possible to minimize
current loops. Use ground planes for best results.
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. Use a multilayer board
whenever possible for better noise immunity and power
dissipation. Follow these guidelines for good PCB layout:
U Use a large contiguous copper plane under the
MAX16833/MAX16833B package. Ensure that all
heat-dissipating components have adequate cooling.
U Isolate the power components and high-current paths
from the sensitive analog circuitry.
U Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable,
jitter-free operation. Keep switching loops short such that:
a) The anode of D1 must be connected very close to
the drain of the MOSFET Q1.
b) The cathode of D1 must be connected very close
to COUT.
c) COUT and current-sense resistor R4 must be con-
nected directly to the ground plane.
U Connect PGND and SGND at a single point.
U Keep the power traces and load connections short. This
practice is essential for high efficiency. Use thick copper
PCBs (2oz vs. 1oz) to enhance full-load efficiency.
U Route high-speed switching nodes away from the
sensitive analog areas. Use an internal PCB layer for
the PGND and SGND plane as an EMI shield to keep
radiated noise away from the device, feedback divid-
ers, and analog bypass capacitors.
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