MAX1192 Datasheet, PDF (19/28 Pages) Maxim Integrated Products – Ultra-Low-Power, 22Msps, Dual 8-Bit ADC

Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
Table 2. Output Codes vs. Input Voltage
DIFFERENTIAL INPUT VOLTAGE
(IN+ - IN-)
V_REF
×
127
128
V_REF
×
126
128
V_REF
×
1
128
V_REF
×
0
128
-V_REF
×
1
128
- V_REF
×
127
128
- V_REF
×
128
128
DIFFERENTIAL INPUT
(LSB)
+127
(+ full scale - 1 LSB)
+126
(+ full scale - 2 LSB)
+1
0 (bipolar zero)
-1
-127
(- full scale + 1 LSB)
- 128 (- full scale)
OFFSET BINARY
(D7–D0)
1111 1111
1111 1110
1000 0001
1000 0000
0111 1111
0000 0001
0000 0000
OUTPUT DECIMAL CODE
255
254
129
128
127
1
0
Table 3. Power Logic
PD0
PD1
POWER MODE
0
0
Shutdown
0
1
Standby
1
0
Idle
1
1
Normal Operating
ADC
Off
Off
On
On
INTERNAL
REFERENCE
Off
On
On
On
CLOCK DISTRIBUTION
Off
On
On
On
OUTPUTS
Tri-state
Tri-state
Tri-state
On
heavy capacitive loads. To improve the dynamic perfor-
mance of the MAX1192, add 100Ω resistors in series
with the digital outputs close to the MAX1192. Refer to
the MAX1193 Evaluation Kit schematic for an example
of the digital outputs driving a digital buffer through
100Ω series resistors.
Power Modes (PD0, PD1)
The MAX1192 has four power modes that are con-
trolled with PD0 and PD1. Four power modes allow the
MAX1192 to efficiently use power by transitioning to a
low-power state when conversions are not required
(Table 3).
Shutdown mode offers the most dramatic power sav-
ings by shutting down all the analog sections of the
MAX1192 and placing the outputs in tri-state. The
wake-up time from shutdown mode is dominated by the
time required to charge the capacitors at REFP, REFN,
and COM. In internal reference mode and buffered
external reference mode, the wake-up time is typically
20µs. When operating in the unbuffered external refer-
ence mode, the wake-up time is dependent on the
external reference drivers. When the outputs transition
from tri-state to on, the last converted word is placed
on the digital outputs.
In standby mode, the reference and clock distribution
circuits are powered up, but the pipeline ADCs are
unpowered and the outputs are in tri-state. The wake-
up time from standby mode is dominated by the 5.4µs
required to activate the pipeline ADCs. When the out-
puts transition from tri-state to on, the last converted
word is placed on the digital outputs.
______________________________________________________________________________________ 19