MAX1026_09 Datasheet, PDF (19/22 Pages) Maxim Integrated Products – 10-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference

10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
DIN
CS
SCLK
(ACQUISITION1)
(CONVERSION BYTE)
(CONVERSION1)
(ACQUISITION2)
DOUT
MSB1
LSB1
MSB2
EOC
EXTERNALLY TIMED ACQUISITION, SAMPLING AND CONVERSION WITHOUT CNVST. X = DON'T CARE.
Figure 7. Clock Mode 11
Externally Clocked Acquisitions and
Conversions Using the Serial Interface
Performing Conversions in Clock Mode 11
In clock mode 11, acquisitions and conversions are ini-
tiated by writing to the conversion register and are per-
formed one at a time using the SCLK as the conversion
clock. Scanning and averaging are disabled, and the
conversion result is available at DOUT during the con-
version. See Figure 7 for clock mode 11 timing.
Initiate a conversion by writing a byte to the conversion
register followed by 16 SCLK cycles. If CS is pulsed
high between the eighth and ninth cycles, the pulse
width must be less than 100μs. To continuously convert
at 16 cycles per conversion, alternate 1 byte of zeros
between each conversion byte.
If reference mode 00 is requested, or if an external refer-
ence is selected but a temperature measurement is
being requested, wait 65μs with CS high after writing the
conversion byte to extend the acquisition and allow the
internal reference to power up. To perform a temperature
measurement, write 24 bytes (192 cycles) of zeros after
the conversion byte. The temperature result appears on
DOUT during the last 2 bytes of the 192 cycles.
Partial Reads and Partial Writes
If the first byte of an entry in the FIFO is partially read
(CS is pulled high after fewer than eight SCLK cycles),
the second byte of data that is read out contains the
next 8 bits (not b7–b0). The remaining bits are lost for
that entry. If the first byte of an entry in the FIFO is read
out fully, but the second byte is read out partially, the
rest of the entry is lost. The remaining data in the FIFO
is uncorrupted and can be read out normally after tak-
ing CS low again, as long as the 4 leading bits (normal-
ly zeros) are ignored. Internal registers that are written
partially through the SPI contain new values, starting at
the MSB up to the point that the partial write is stopped.
The part of the register that is not written contains previ-
ously written values. If CS is pulled low before EOC
goes low, a conversion cannot be completed and the
FIFO is corrupted.
Transfer Function
Figure 8 shows the unipolar transfer function for single-
ended or differential inputs. Figure 9 shows the bipolar
transfer function for differential inputs. Code transitions
occur halfway between successive-integer LSB values.
Output coding is binary, with 1 LSB = V_REF / 1024V for
unipolar and bipolar operation, and 1 LSB = 0.125°C
for temperature measurements.
Layout, Grounding, and Bypassing
For best performance, use PC boards. Do not use wire-
wrap boards. For the TQFN package, connect its
exposed pad to GND. Board layout should ensure that
digital and analog signal lines are separated from each
other. Do not run analog and digital (especially clock)
signals parallel to one another or run digital lines under-
neath the MAX1026/MAX1028/MAX1030 package. High-
frequency noise in the V_DD power supply can affect
performance. Bypass the V_DD supply with a 0.1μF
capacitor to GND, close to the V_DD pin. Minimize
capacitor lead lengths for best supply-noise rejection. If
the power supply is very noisy, connect a 10Ω resistor in
series with the supply to improve power-supply filtering.
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