DS26521 Datasheet, PDF (183/258 Pages) Maxim Integrated Products – Single T1/E1/J1 Transceiver

DS26521 Single T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
TCR2 (T1 Mode)
Transmit Control Register 2
182h
Bit #
7
6
5
Name
TFDLS TSLC96
—
Default
0
0
0
Note: See TCR2 for E1 mode.
4
FBCT2
0
3
FBCT1
0
2
TD4RM
0
1
PDE
0
0
TB7ZS
0
Bit 7: TFDL Register Select (TFDLS).
0 = source FDL or Fs bits from the internal TFDL register or the SLC-96 data formatter (TCR2.6)
1 = source FDL or Fs bits from the internal HDLC controller
Bit 6: Transmit SLC-96 (TSLC96). Set this bit to a one in SLC-96 framing applications. Must be set to source the
SLC-96 alignment pattern and data from the T1TSLC1:T1TSLC3 registers. See Section 8.9.4.4 for details.
0 = SLC-96 insertion disabled
1 = SLC-96 insertion enabled
Bit 4: F-Bit Corruption Type 2 (FBCT2). Setting this bit high enables the corruption of one Ft (D4 framing mode)
or FPS (ESF framing mode) bit in every 128 Ft or FPS bits as long as the bit remains set.
Bit 3: F-Bit Corruption Type 1 (FBCT1). A low-to-high transition of this bit causes the next three consecutive Ft
(D4 framing mode) or FPS (ESF framing mode) bits to be corrupted causing the remote end to experience a loss of
synchronization.
Bit 2: Transmit D4 RAI Select (TD4RM).
0 = zeros in bit 2 of all channels
1 = a one in the S-bit position of frame 12
Bit 1: Pulse Density Enforcer Enable (PDE). The framer always examines both the transmit and receive data
streams for violations of the following rules which are required by ANSI T1.403: no more than 15 consecutive zeros
and at least N ones in each and every time window of 8 x (N +1) bits where N = 1 through 23. Violations for the
transmit and receive data streams are reported in the TLS1.3 and RLS2.7 bits, respectively. When this bit is set to
one, the DS26521 will force the transmitted stream to meet this requirement no matter the content of the
transmitted stream. When running B8ZS, this bit should be set to zero since B8ZS-encoded data streams cannot
violate the pulse density requirements.
0 = disable transmit pulse density enforcer
1 = enable transmit pulse density enforcer
Bit 0: Transmit-Side Bit 7 Zero-Suppression Enable (TB7ZS).
0 = no stuffing occurs
1 = force bit 7 to a one as determined by the GB7S bit at TCR1.3
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