MAX8655_09 Datasheet, PDF (18/23 Pages) Maxim Integrated Products – Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator

Highly Integrated, 25A, Wide-Input,
Internal MOSFET, Step-Down Regulator
inductor and output capacitor resulting in a smaller
phase shift and requiring a less elaborate error-amplifier
compensation than voltage-mode control. A simple
series R_C and C_C is all that is needed to have a stable,
high-bandwidth loop in applications where ceramic
capacitors are used for output filtering. For other types
of capacitors, due to the higher capacitance and ESR,
the frequency of the zero created by the capacitance
and ESR is lower than the desired closed-loop crossover
frequency. To stabilize a nonceramic output-capacitor
loop, add another compensation capacitor from COMP
to GND to cancel this ESR zero. See Figure 9.
The basic regulator loop is modeled as a power modu-
lator, an output feedback divider, and an error amplifi-
er. The power modulator has DC gain G_MOD(dc), set by
g_mc x R_LOAD, with a pole and zero pair set by R_LOAD,
the output capacitor (C_OUT), and its equivalent series
resistance (ESR). Below are equations that define the
power modulator:
[^{( )} ] ^{( ) GMOD(dc)}
= g_mc
×
⎡⎢₁₊
⎣
R_LOAD
L × f_S
R_LOAD
× K_S ×
1− D
−
0.5
⎤
⎥
⎦
where R_LOAD = V_OUT / I_OUT(MAX), f_S is the switching
frequency, L is the output inductance, g_mc = 1 / (A_VCS x
R_L), where A_VCS is the gain of the current-sense amplifi-
er (12 typ), R_L is the DC resistance of the inductor, the
duty cycle D = V_OUT / V_IN. K_S is a slope compensation
factor calculated from the following equation:
K_S
=
1+
V_SCOMP × L × f_S
120 × (V_IN − V_OUT) ×
R_L
When SCOMP is connected to GND, use V_SCOMP = 1.25V;
when SCOMP is connected to AVL, use V_SCOMP = 2.5V.
Find the pole and zero frequencies created by the
power modulator as follows:
f_pMOD
=
1
2π × R_LOAD
× C_OUT
+
[ ] ^⎡
1
⎢
⎣
2π
×
L
×
f_S
× C_OUT
×
K_S
× (1− D) − 0.5
⎤
⎥
⎦
COMP
MAX8655
C_F
R_C
C_C
f_zMOD
=
2π
×
1
C_OUT
×
ESR
When C_OUT comprises “n” identical capacitors in paral-
lel, the resulting C_OUT = n x C_OUT(EACH), and ESR =
ESR_(EACH) / n. Note that the capacitor zero for a paral-
lel combination of like capacitors is the same as for an
individual capacitor. Figure 10 is the simplified gain
plot for the f_zMOD > f_C case.
The feedback voltage-divider has a gain of G_FB = V_FB /
V_OUT, where V_FB is equal to 0.7V.
The transconductance error amplifier has a DC gain,
G_EA(DC) = g_mEA x R_O, where g_mEA is the error-amplifi-
er transconductance, which is equal to 110µS, and R_O
is the output resistance of the error amplifier, which is
30MΩ. A dominant pole (f_pdEA) is set by the compen-
sation capacitor (C_C), the amplifier output resistance
(R_O), and the compensation resistor (R_C); a zero (f_zEA)
is set by the compensation resistor (R_C) and the com-
pensation capacitor (C_C). There is an optional pole
(f_pEA) set by C_F and R_C to cancel the output capacitor
ESR zero if it occurs near the crossover frequency (f_C).
Thus:
f_pdEA
=
2π
×
C_C
1
× (R_O
+ R_C)
f_zEA
=
2π
×
1
C_C
× R_C
f_pEA
=
2π
×
1
C_F
× R_C
GAIN
(dB)
POWER
MODULATOR
0dB
FB
DIVIDER
CLOSED LOOP
fp_MOD
ERROR
AMPLIFIER
fc
FREQUENCY
fz_MOD
Figure 9. Compensation Components
Figure 10. Simplified Gain Plot for the fzMOD > fC Case
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