MAX16821A_10 Datasheet, PDF (18/24 Pages) Maxim Integrated Products – High-Power Synchronous HBLED Drivers with Rapid Current Pulsing

High-Power Synchronous HBLED
Drivers with Rapid Current Pulsing
Inductor Selection
The switching frequency, peak inductor current, and
allowable ripple at the output determine the value and
size of the inductor. Selecting higher switching frequen-
cies reduces inductance requirements, but at the cost
of efficiency. The charge/discharge cycle of the gate
and drain capacitance in the switching MOSFETs cre-
ate switching losses worsening at higher input volt-
ages, since switching losses are proportional to the
square of the input voltage. The MAX16821A/
MAX16821B/MAX16821C operate up to 1.5MHz.
Choose inductors from the standard high-current, sur-
face-mount inductor series available from various manu-
facturers. Particular applications may require
custom-made inductors. Use high-frequency core mate-
rial for custom inductors. High ∆I_L causes large peak-to-
peak flux excursion increasing the core losses at higher
frequencies. The high-frequency operation coupled with
high ∆I_L reduces the required minimum inductance and
makes the use of planar inductors possible.
The following discussion is for buck or continuous
boost-mode topologies. Discontinuous boost, buck-
boost, and SEPIC topologies are quite different in
regards to component selection. Use the following
equations to determine the minimum inductance value:
Buck regulators:
( ) _{LMIN =}
V_INMAX − V_LED × V_LED
V_INMAX × f_SW × ∆I_L
Boost regulators:
( ) _{LMIN =}
V_LED − V_INMAX × V_INMAX
V_LED × f_SW × ∆I_L
where V_LED is the total voltage across the LED string.
The average current-mode control feature of the
MAX16821A/MAX16821B/MAX16821C limits the maxi-
mum peak inductor current and prevents the inductor
from saturating. Choose an inductor with a saturating
current greater than the worst-case peak inductor cur-
rent. Use the following equation to determine the worst-
case current in the average current-mode control loop.
I_LPEAK
=
V_CL
R_S
+
⎛
⎝⎜
∆I_CL
2
⎞
⎠⎟
where R_S is the sense resistor and V_CL = 0.030V. For
the buck converter, the sense current is the inductor
current and for the boost converter, the sense current is
the input current.
Switching MOSFETs
When choosing a MOSFET for voltage regulators, con-
sider the total gate charge, R_DS(ON), power dissipation,
and package thermal impedance. The product of the
MOSFET gate charge and on-resistance is a figure of
merit, with a lower number signifying better perfor-
mance. Choose MOSFETs optimized for high-frequen-
cy switching applications. The average current from the
MAX16821A/MAX16821B/MAX16821C gate-drive out-
put is proportional to the total capacitance it drives
from DH and DL. The power dissipated in the
MAX16821A/MAX16821B/MAX16821C is proportional
to the input voltage and the average drive current. The
gate charge and drain capacitance losses (CV²), the
cross-conduction loss in the upper MOSFET due to
finite rise/fall time, and the I²R loss due to RMS current
in the MOSFET R_DS(ON) account for the total losses in
the MOSFET. Estimate the power loss (PD_{MOS_}) in the
high-side and low-side MOSFETs using the following
equations:
( ) PD_{MOS_HI} = Q_G × V_DD × f_SW +
( ) ^⎡
⎢
V_IN
×
I_LED
×
t_R + t_f
×
f_SW
⎤
⎥
+
⎣⎢
2
⎦⎥
R_DSON × I^2RMS_−HI
where Q_G, R_DS(ON), t_R, and t_F are the upper-switching
MOSFET’s total gate charge, on-resistance, rise time,
and fall time, respectively.
I_RMS−HI =
⎛⎝_I² _VALLEY
+ I^2PK
+ I_VALLEY
×
I_PK
⎞
⎠
×
D
3
For the buck regulator, D is the duty cycle, I_VALLEY =
(I_OUT - ∆I_L / 2) and I_PK = (I_OUT + ∆I_L / 2).
( ) PD_{MOS_LO} = Q_G × V_DD × f_SW + R_DSON × I^2RMS−LO
( ) _{IRMS−LO =}
⎛⎝_I2 _VALLEY
+ I^2PK
+ I_VALLEY
×
I_PK
⎞
⎠
×
1− D
3
Input Capacitors
The discontinuous input-current waveform of the buck
converter causes large ripple currents in the input
capacitor. The switching frequency, peak inductor cur-
rent, and the allowable peak-to-peak voltage ripple
reflected back to the source dictate the capacitance
requirement. The input ripple is comprised of ∆V_Q
(caused by the capacitor discharge) and ∆V_ESR
(caused by the ESR of the capacitor).
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