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MAX15053 Datasheet, PDF (18/21 Pages) Maxim Integrated Products – High-Efficiency, 2A, Current-Mode Synchronous, Step-Down Switching Regulator | |||
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High-Efficiency, 2A, Current-Mode
Synchronous, Step-Down Switching Regulator
RC
=
R1+ R2
R2
Ã

ï£ï£¬ï£¬1+
RLOADK S (1â D)
L Ã fSW
â
0.5


gMV Ã gMC Ã RLOAD
Ã
2ÏfCOC OUT
Ã





ESR +




ï£
1
RLOAD
+
1

K
S
(1â
LÃ
D) â
fSW
0.5

and where the ESR is much smaller than the parallel
combination of the equivalent load resistance and the
current loop impedance, e.g.,:
ESR <<
1
ï£«ï£¬ï£¬ï£ RLO1AD
+
K
S
(1â
LÃ
D) â
fSW
0.5


RC becomes:
RC
=
R1+ R2
R2
Ã
2ÏfCO Ã COUT
gMV Ã gMC
3) Determine CC by selecting the desired first sys-
tem zero, fZ1, based on the desired phase margin.
Typically, setting fZ1 below 1/5 of fCO provides suf-
ficient phase margin.
fZ1
=
2Ï
Ã
1
C CR C
â¤
fCO
5
therefore:
CC
â¥
2Ï
Ã
5
fCO
Ã
RC
4) For low duty-cycle applications, the addition of a
phase-leading capacitor (CFF in Figure 1) helps
mitigate the phase lag of the damped half-frequency
double pole. Adding a second zero near to but below
the desired crossover frequency increases both the
closed-loop phase margin and the regulatorâs unity-
gain bandwidth (crossover frequency). Select the
capacitor as follows:
CFF
=
2Ï Ã
1
fCO Ã
(R1|| R2)
Using CFF the zero-pole order is adjusted as follows:
fP1
<
fP2
â¤
fZ1
<
1
2ÏCFFR1
<
1
2ÏCFF (R1|| R2)
â
fCO < fP3 < fZ2
Confirm the desired operation of CFF empirically. The
phase lead of CFF diminishes as the output voltage
is a smaller multiple of the reference voltage, e.g.,
below about 1V. Do not use CFF when VOUT = VFB.
Setting the Soft-Start Time
The soft-start feature ramps up the output voltage slowly,
reducing input inrush current during startup. Size the
CSS capacitor to achieve the desired soft-start time, tSS,
using:
C SS
=
ISS Ã t SS
VFB
ISS, the soft-start current, is 10FA (typ) and VFB, the
output feedback voltage threshold, is 0.6V (typ). When
using large COUT capacitance values, the high-side
current limit can trigger during the soft-start period. To
ensure the correct soft-start time, tSS, choose CSS large
enough to satisfy:
C SS
>>
C OUT
Ã
VOUT ÃISS
(IHSCL_ â IOUT ) Ã
VFB
IHSCL_ is the typical high-side MOSFET current-limit
value.
An external tracking reference with steady-state value
between 0V and VIN - 1.8V can be applied to SS/REFIN.
In this case, connect an RC network from external track-
ing reference and SS/REFIN, as shown in Figure 4. The
recommended value for RSS is approximately 1kI.
RSS is needed to ensure that, during hiccup period,
SS/REFIN can be internally pulled down.
When an external reference is connected to SS/REFIN,
the soft-start must be provided externally.
VREF_EXT
RSS
CSS
SS/REFIN
MAX15053
This guarantees the additional phase-leading zero
occurs at a frequency lower than fCO from:
fPHASE_LEAD
=
2Ï
Ã
1
CFF
à R1
Figure 4. RC Network for External Reference at SS/REFIN
18ââ
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