MAX14950A Datasheet, PDF (18/20 Pages) Maxim Integrated Products – Single-Lane PCIe Equalizer/Redriver

MAX14950A
Single-Lane PCIe Equalizer/Redriver
Applications Information
Layout
Circuit board layout and design can significantly affect
the performance of the device. Use good high-frequency
design techniques, including minimizing ground induc-
tance and using controlled-impedance transmission lines
on data signals. Power-supply decoupling capacitors
must be placed as close as possible to V_CC. Always
connect V_CC to a power plane. It is recommended to
run receive and transmit on different layers to minimize
crosstalk.
Exposed-Pad Package
The exposed-pad, 40-pin TQFN package incorporates
features that provide a very low thermal resistance
path for heat removal from the IC. The exposed pad
on the device must be soldered to the circuit board
ground plane for proper thermal performance. For more
information on exposed-pad packages, refer to Maxim
Application Note HFAN-08.1: Thermal Considerations of
QFN and Other Exposed-Paddle Packages.
Power-Supply Sequencing
Caution: Do not exceed the absolute maximum rat-
ings because stresses beyond the listed ratings
could cause permanent damage to the device.
Proper power-supply sequencing is recommended for all
devices. Always apply GND then V_CC before applying
signals, especially if the signal is not current limited.
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX14950ACTL+ 0NC to +70NC
40 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
PROCESS: BiCMOS
Chip Information
Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
40 TQFN-EP
PACKAGE
CODE
T4055+2
OUTLINE
NO.
21-0140
LAND
PATTERN NO.
90-0002
Maxim Integrated
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