MAX14578E_12 Datasheet, PDF (18/23 Pages) Maxim Integrated Products – USB Battery Charger Detectors

MAX14578E/MAX14578AE
USB Battery Charger Detectors
Bit Transfer
One data bit is transferred during each clock pulse
(Figure 6). The data on SDA must remain stable while
SCL is high.
Acknowledge
The acknowledge bit is a clocked 9th bit that the
recipient uses to handshake receipt of each byte of
data (Figure 7). Thus, each byte transferred effectively
requires nine bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse. The SDA line is stable low
during the high period of the clock pulse. When the
master is transmitting to the MAX14578E, it generates
the acknowledge bit because the MAX14578E is the
recipient. When the MAX14578E is transmitting to the
master, the master generates the acknowledge bit
because the master is the recipient.
Slave Address
The MAX14578E has a 7-bit long slave address. The bit
following a 7-bit slave address is the R/W bit, which is
low for a write command and high for a read command.
The slave address is 01011001 for read commands and
01011000 for write commands. See Figure 8.
Bus Reset
The MAX14578E resets the bus with the I²C START
condition for reads. When the R/W bit is set to 1, the
MAX14578E transmits data to the master, thus the mas-
ter is reading from the device.
SDA
SCL
Figure 6. Bit Transfer
DATA LINE STABLE;
DATA VALID
START
CONDITION
SCL
1
SDA
BY
TRANSMITTER
SDA
BY
RECEIVER
S
Figure 7. Acknowledge
CHANGE OF DATA
ALLOWED
2
SDA
0
1
0
1
MSB
SCL
Figure 8. Slave Address
18  
1
0
CLOCK PULSE FOR
ACKNOWLEDGE
8
9
0
R/W
ACK
LSB
Maxim Integrated