MAX1444 Datasheet, PDF (18/20 Pages) Maxim Integrated Products – 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference

10-Bit, 40Msps, 3.0V, Low-Power
ADC with Internal Reference
power-supply sequencing when powering up or down.
With the outputs of the MAX4252 matching better than
0.1%, the buffers and subsequent lowpass filters can
be replicated to support as many as 32 ADCs. For
applications that require more than 32 matched ADCs,
a voltage reference and divider string common to all
converters is highly recommended.
Grounding, Bypassing,
and Board Layout
The MAX1444 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side as
the ADC, using surface-mount devices for minimum
inductance. Bypass V_DD, REFP, REFN, and COM with
two parallel 0.1µF ceramic capacitors and a 2.2µF
bipolar capacitor to GND. Follow the same rules to
bypass the digital supply (OV_DD) to OGND. Multilayer
boards with separated ground and power planes pro-
duce the highest level of signal integrity. Consider
using a split ground plane arranged to match the physi-
cal location of the analog ground (GND) and the digital
output driver ground (OGND) on the ADC's package.
The two ground planes should be joined at a single
point so that the noisy digital ground currents do not
interfere with the analog ground plane. The ideal loca-
tion of this connection can be determined experimen-
tally at a point along the gap between the two ground
planes that produces optimum results. Make this con-
nection with a low-value, surface-mount resistor (1Ω to
5Ω), a ferrite bead, or a direct short. Alternatively, all
ground pins could share the same ground plane if the
ground plane is sufficiently isolated from any noisy, dig-
ital systems ground plane (e.g., downstream output
buffer or DSP ground plane). Route high-speed digital
signal traces away from sensitive analog traces. Keep
all signal lines short and free of 90° turns.
Static Parameter Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best straight-line fit or a line
drawn between the endpoints of the transfer function
once offset and gain errors have been nullified. The
MAX1444’s static linearity parameters are measured
using the best straight-line fit method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
Dynamic Parameter Definitions
Aperture Jitter
Figure 12 depicts the aperture jitter (t_AJ), which is the
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (t_AD) is the time defined between the
falling edge of the sampling clock and the instant when
an actual sample is taken (Figure 12).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum A/D noise is caused by quantization error only
and results directly from the ADC’s resolution (N bits):
SNR_(MAX) = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
CLK
ANALOG
INPUT
t_AD
t_AJ
SAMPLED
DATA (T/H)
T/H ^TRACK
HOLD
Figure 12. T/H Aperture Timing
TRACK
18 ______________________________________________________________________________________