DS8005 Datasheet, PDF (18/20 Pages) Maxim Integrated Products – Smart Card Intergace

Smart Card Interface
Applications Information
Performance can be affected by the layout of the appli-
cation. For example, an additional cross-capacitance of
1pF between card reader contacts C2 (RST_) and C3
(CLK_) or C2 (RST_) and C7 (I/O_) can cause contact
C2 to be polluted with high-frequency noise from C3 (or
C7). In this case, include a 100pF capacitor between
contacts C2 and CGND.
Application recommendations include the following:
• Ensure there is ample ground area around the device
and the connector; place the device very near to the
connector; decouple the V_DD and V_DDA lines sepa-
rately. These lines are best positioned under the con-
nector.
• The device and the host microcontroller must use the
same V_DD supply. Pins CLKDIV1, CLKDIV2, RSTIN,
PRES_, I/OIN, 5V/3V, 1_8V, CMDVCC, and OFF are
referenced to V_DD; if pin XTAL1 is to be driven by an
external clock, also reference this pin to V_DD.
• Trace C3 (CLK) should be placed as far as possible
from the other traces.
• The trace connecting CGND to C5 (GND) should be
straight (the two capacitors on C1 (V_{CC_}) should be
connected to this ground trace).
• Avoid ground loops between CGND and GND.
• Decouple V_DDA and V_DD separately. If two supplies
are the same in the application, they should be con-
nected in a star on the main trace
With all these layout precautions, noise should be kept to
an acceptable level and jitter on C3 (CLK_) should be
less than 100ps. Reference layouts are available on
request.
Technical Support
For technical support, go to https://support.maxim-
ic.com/micro.
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