MAX9598_09 Datasheet, PDF (17/36 Pages) Maxim Integrated Products – Low-Power Audio/Video Switch for Dual SCART Connectors

Low-Power Audio/Video Switch for
Dual SCART Connectors
Fast Switching
The fast-switching signal was originally used to switch
between CVBS and RGB signals on a pixel-by-pixel
basis so that on-screen display (OSD) information
could be inserted. Since modern set-top box decoder
chips have integrated OSD circuitry, there is no need to
create OSD information using the older technique.
Now, the fast-switching signal is just used to switch
between CVBS and RGB signal sources.
Set the source of the fast-switching signal by writing to
bits 4 and 3 of the TV Video Output Control Register
(07h). The fast switching signal to the TV SCART con-
nector can be enabled or disabled by bit 1 of the Output
Enable Register (0Dh). See Tables 8, 13, and 16.
I²C Serial Interface
The MAX9598 features an I²C/SMBus™-compatible, 2-
wire serial interface consisting of a serial data line (SDA)
and a serial clock line (SCL). SDA and SCL facilitate
communication between the MAX9598 and the master
at clock rates up to 400kHz. Figure 6 shows the 2-wire
interface timing diagram. The master generates SCL
and initiates data transfer on the bus. A master device
writes data to the MAX9598 by transmitting a START (S)
condition, the proper slave address with the R/W bit set
to 0, followed by the register address and then the data
word. Each transmit sequence is framed by a START (S)
and a STOP (P) condition. Each word transmitted to the
MAX9598 is 8 bits long and is followed by an acknowl-
edge clock pulse. A master reads from the MAX9598 by
transmitting the slave address with the R/W bit set to 0,
the register address of the register to be read, a
REPEATED START (Sr) condition, the slave address with
the R/W bit set to 1, followed by a series of SCL pulses.
The MAX9598 transmits data on SDA in sync with the
master-generated SCL pulses. The master acknowl-
edges receipt of each byte of data. Each read
sequence is framed by a START (S) or REPEATED
START (Sr) condition, an acknowledge or a not acknowl-
edge, and a STOP (P) condition. SDA operates as both
an input and an open-drain output. A pullup resistor,
typically greater than 500Ω, is required on the SDA bus.
SCL operates as only an input. A pullup resistor, typical-
ly greater than 500Ω, is required on SCL if there are
multiple masters on the bus, or if the master in a single-
master system has an open-drain SCL output. Series
resistors in line with SDA and SCL are optional. Series
resistors protect the digital inputs of the MAX9598 from
high-voltage spikes on the bus lines, and minimize
crosstalk and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section). SDA and SCL idle high when the
I²C bus is not busy.
SDA
t_{SU, DAT}
t_LOW
t_{HD, DAT}
SCL
t_{HD, STA}
START
CONDITION
t_HIGH
t_R
t_F
Figure 6. I²C Serial-Interface Timing Diagram
t_{SU, STA}
t_{SU, STA}
REPEATED
START CONDITION
t_BUF
t_{SP tSU, STO}
STOP
START
CONDITION CONDITION
SMBus is a trademark of Intel Corporation.
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