MAX5065 Datasheet, PDF (17/32 Pages) Maxim Integrated Products – Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers

Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
where, Q_G1, Q_G2, Q_G3, and Q_G4 are the total gate
charge of the low-side and high-side external
MOSFETs, I_Q is 4mA (typ), and f_SW is the switching fre-
quency of each individual phase.
For applications utilizing a +5V input voltage, disable
the V_CC regulator by connecting IN and V_CC together.
Undervoltage Lockout (UVLO)/Soft-Start
The MAX5065/MAX5067 include an undervoltage lock-
out with hysteresis and a power-on reset circuit for con-
verter turn-on and monotonic rise of the output voltage.
The UVLO threshold is internally set between +4.0V
and +4.5V with a 200mV hysteresis. Hysteresis at
UVLO eliminates “chattering” during startup.
Most of the internal circuitry, including the oscillator,
turns on when the input voltage reaches +4V. The
MAX5065/MAX5067 draw up to 4mA of current before
the input voltage reaches the UVLO threshold.
The compensation network at the current-error ampli-
fiers (CLP1 and CLP2) provides an inherent soft-start of
the output voltage. It includes a parallel combination of
capacitors (C34, C36) and resistors (R5, R6) in series
with other capacitors (C33, C35) (see Figures 1 and 2).
The voltage at CLP_ limits the maximum current avail-
able to charge output capacitors. The capacitor on
CLP_ in conjunction with the finite output-drive current
of the current-error amplifier yields a finite rise time for
the output current and thus the output voltage.
Internal Oscillator
The internal oscillator generates the 180° out-of-phase
clock signals required by the pulse-width modulation
(PWM) circuits. The oscillator also generates the 2V_P-P
voltage ramp signals necessary for the PWM compara-
tors. Connect CLKIN to SGND to set the internal oscillator
frequency to 250kHz or connect CLKIN to V_CC to set the
internal oscillator to 500kHz.
CLKIN is a CMOS logic clock input for the phase-
locked loop (PLL). When driven externally, the internal
oscillator locks to the signal at CLKIN. A rising edge at
CLKIN starts the ON cycle of the PWM. Ensure that the
external clock pulse width is at least 200ns. CLKOUT
provides a phase-shifted output with respect to the ris-
ing edge of the signal at CLKIN. PHASE sets the
amount of phase shift at CLKOUT. Connect PHASE to
V_CC for 120° of phase shift, leave PHASE unconnected
for 90° of phase shift, or connect PHASE to SGND for
60° of phase shift with respect to CLKIN.
The MAX5065/MAX5067 require compensation on
PLLCMP even when operating from the internal oscillator.
The device requires an active PLL to generate the proper
clock signal required for PWM operation.
Control Loop
The MAX5065/MAX5067 use an average-current-mode
control scheme to regulate the output voltage (Figure
4). The main control loop consists of an inner current
loop and an outer voltage loop. The inner loop controls
the output currents (I_PHASE1 and I_PHASE2) while the
outer loop controls the output voltage. The inner current
loop absorbs the inductor pole reducing the order of
the outer voltage loop to that of a singlepole system.
The current loop consists of a current-sense resistor
(R_S), a current-sense amplifier (CA_), a current-error
amplifier (CEA_), an oscillator providing the carrier
ramp, and a PWM comparator (CPWM_). The precision
CA_ amplifies the sense voltage across R_S by a factor
of 18. The inverting input to the CEA_ senses the CA_
output. The CEA_ output is the difference between the
voltage-error amplifier output (EAOUT) and the gained-
up voltage from the CA_. The RC compensation net-
work connected to CLP1 and CLP2 provides external
frequency compensation for the respective CEA_. The
start of every clock cycle enables the high-side drivers
and initiates a PWM ON cycle. Comparator CPWM_
compares the output voltage from the CEA_ with a 0 to
+2V ramp from the oscillator. The PWM ON cycle termi-
nates when the ramp voltage exceeds the error voltage.
The outer voltage control loop consists of the differen-
tial amplifier (DIFF AMP), reference voltage, and VEA.
The unity-gain differential amplifier provides true differ-
ential remote sensing of the output voltage. The differ-
ential amplifier output connects to the inverting input
(EAN) of the VEA. The noninverting input of the VEA is
internally connected to an internal precision reference
voltage. The MAX5067 reference voltage is set to +0.8V
and the MAX5065 reference is set to +0.6V. The VEA
controls the two inner current loops (Figure 4). Use a
resistive feedback network to set the VEA gain as
required by the adaptive voltage-positioning circuit
(see the Adaptive Voltage Positioning section).
Current-Sense Amplifier
The differential current-sense amplifier (CA_) provides a
DC gain of 18. The maximum input offset voltage of the
current-sense amplifier is 1mV and the common-mode
voltage range is -0.3V to +3.6V. The current-sense ampli-
fier senses the voltage across a current-sense resistor.
Peak-Current Comparator
The peak-current comparator provides a path for fast
cycle-by-cycle current limit during extreme fault condi-
tions such as an output inductor malfunction (Figure 5).
Note that the average current-limit threshold of 48mV
still limits the output current during short-circuit condi-
tions. To prevent inductor saturation, select an output
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