MAX17075 Datasheet, PDF (17/22 Pages) Maxim Integrated Products – Boost Regulator with Integrated Charge Pumps, Switch Control, and High-Current Op Amp

Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
Reference Voltage (REF)
The reference voltage is nominally 1.25V, and can
source at least 50µA (see the Typical Operating
Characteristics). V_CC is the input of the internal refer-
ence block. Bypass REF with a 0.22µF ceramic capaci-
tor connected between REF and AGND.
Power-Up Sequence and Soft-Start
Once the voltage on V_CC exceeds the XAO UVLO
threshold of approximately 1.5V, the reference turns on.
With a 0.22µF REF bypass capacitor, the reference
reaches its regulation voltage of 1.25V in approximately
1ms. When the reference voltage exceeds 1V and V_CC
exceeds its UVLO threshold of approximately 2.25V,
the IC enables the main step-up regulator, the gate-on
linear-regulator controller, and the gate-off linear-
regulator controller simultaneously.
The IC employs soft-start for each regulator to minimize
inrush current and voltage overshoot and to ensure a
well-defined startup behavior. Each output uses a 7-bit
soft-start DAC. For the step-up and the gate-on linear
regulator, the DAC output is stepped in 128 steps from
zero up to the reference voltage. For the gate-off linear
regulator, the DAC output steps from the reference
down to 250mV in 128 steps. The soft-start duration is
10ms (typ) for step-up regulator and 3ms (typ) for gate-
on and gate-off regulators.
A capacitor (C_DEL) from DEL to AGND determines the
switch-control-block startup delay. After the input volt-
age exceeds the UVLO threshold (2.25V typ) and the
soft-start routine for each regulator is complete and
there is no fault detected, a 5mA current source starts
charging C_DEL. Once the capacitor voltage exceeds
1.25V (typ), the switch-control block is enabled as
shown in Figure 8. After the switch-control block is
enabled, COM can be connected to SRC or DRN
through the internal p-channel switches, depending
upon the state of CTL. Before startup and when V_IN is
less than UVLO, DEL is internally connected to AGND
to discharge C_DEL. Select C_DEL to set the delay time
using the following equation:
C_DEL
=
DELAY _ TIME ×
5µA
1.25V
When the input voltage falls below the UVLO falling
threshold, the controller turns off the main step-up regu-
lator and disables the switch-control block; the opera-
tional amplifier output is high impedance.
Fault Protection
During steady-state operation, if the output of the main
regulator or any of the linear-regulator outputs exceed
their respective fault-detection thresholds, the
MAX17075 activates an internal fault timer. If any condi-
tion or combination of conditions indicates a continuous
fault for the fault-timer duration (50ms typ), the
MAX17075 sets the fault latch to shut down all the out-
puts except the reference. Once the fault condition is
removed, cycle the input voltage (below the UVLO
falling threshold) to clear the fault latch and reactivate
the device. The fault-detection circuit is disabled during
the soft-start time.
2.25V
1.5V
1V
VVCC
VREF
VAVDD
14ms ^SOFT-START
VCOM
3ms SOFT-START
VPOUT
1.25V
VGOFF
VDEL
Undervoltage Lockout (UVLO)
The UVLO circuit compares the input voltage at V_CC
with the UVLO threshold (2.25V rising, 2.20V falling, typ)
SOFT-START BEGINS
VGON
to ensure the input voltage is high enough for reliable
operation. The 50mV (typ) hysteresis prevents supply
transients from causing a restart. Once the input voltage
INPUT
VOLTAGE
SWITCH
CONTROL
exceeds the UVLO rising threshold, startup begins.
OK
ENABLED
Figure 8. Power-Up Sequence
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