MAX17003A Datasheet, PDF (17/36 Pages) Maxim Integrated Products – High-Efficiency, Quad-Output, Main Power- Supply Controllers for Notebook Computers

High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
Table 3. Operating Mode Truth Table
MODE
Shutdown Mode
Standby Mode
Normal Operation
3.3V SMPS Active
5V SMPS Active
SHDN
Low
High
High
High
INPUTS*
ON5
X
Low
High
Low
High
High
ON3
X
Low
High
High
Low
LDO5
OFF
ON
ON
ON
OUTPUTS
5V SMPS
OFF
OFF, DSCHG5 LOW
ON
OFF, DSCHG5 LOW
OFF
LDO5 to CSL5 bypass ON
switch enabled
3V SMPS
OFF
OFF, DSCHG3 LOW
ON
ON
OFF, DSCHG3 LOW
Normal Operation
OFF
ON
(Delayed 5V SMPS
High
Ref
High LDO5 to CSL5 bypass Power-up after 3.3V ON
Startup)
switch enabled
SMPS is in regulation
Normal Operation
(Delayed 3.3V SMPS
Startup)
High
High
OFF
Ref LDO5 to CSL5 bypass ON
switch enabled
ON
Power-up after 5V
SMPS is in regulation
*SHDN is an accurate, low-voltage logic input with 1V falling-edge threshold voltage and 1.6V rising-edge threshold voltage. ON3
and ON5 are tri-level CMOS logic inputs, a logic-low voltage is less than 0.8V, a logic-high voltage is greater than 2.4V, and the mid-
dle-logic level is between 1.7V and 2.3V (see the Electrical Characteristics table).
making the threshold to exit shutdown less accurate. To
guarantee startup, drive SHDN above 2V (SHDN input
rising-edge trip level). For automatic shutdown and
startup, connect SHDN to V_IN. The accurate 1V falling-
edge threshold on SHDN can be used to detect a spe-
cific input voltage level and shut the device down. Once
in shutdown, the 1.6V rising-edge threshold activates,
providing sufficient hysteresis for most applications (see
Table 3).
SMPS POR, UVLO, and Soft-Start
Power-on reset (POR) occurs when LDO5 rises above
approximately 1V, resetting the undervoltage, overvolt-
age, and thermal-shutdown fault latches. The POR cir-
cuit also ensures that the low-side drivers are pulled
high until the SMPS controllers are activated. Figure 2
is the MAX17003A/MAX17004A block diagram.
The LDO5 input undervoltage-lockout (UVLO) circuitry
inhibits switching if the 5V bias supply (LDO5) is below
its 4V UVLO threshold. Once the 5V bias supply
(LDO5) rises above this input UVLO threshold and the
SMPS controllers are enabled (ON_ driven high), the
SMPS controllers start switching, and the output volt-
ages begin to ramp up using soft-start. If the LDO5
voltage drops below the UVLO threshold, the controller
stops switching and pulls the low-side gate drivers low
until the LDO5 voltage recovers or drops below the
POR threshold.
The internal soft-start gradually increases the feedback
voltage with a 1V/ms slew rate. Therefore, the outputs
reach their nominal regulation voltage 2ms after the
SMPS controllers are enabled (see the Soft-Start
Waveform in the Typical Operating Characteristics).
This gradual slew rate effectively reduces the input
surge current by minimizing the current required to
charge the output capacitors (I_OUT = I_LOAD + C_OUT x
V_OUT(NOM)/t_SLEW).
SMPS Enable Controls (ON3, ON5)
ON3 and ON5 control SMPS power-up sequencing.
ON3 or ON5 rising above 2.4V enables the respective
outputs. ON3 or ON5 falling below 1.6V disables the
respective outputs. Driving ON_ below 0.8V clears the
overvoltage, undervoltage, and thermal-fault latches.
SMPS Power-Up Sequencing
Connecting ON3 or ON5 to REF forces the respective
outputs off while the other output is below regulation
and starts after that output regulates. The second
SMPS remains on until the first SMPS turns off, the
device shuts down, a fault occurs, or LDO5 goes into
UVLO. Both supplies begin their power-down
sequence immediately when the first supply turns off.
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