MAX1516 Datasheet, PDF (17/26 Pages) Maxim Integrated Products – TFT-LCD DC-DC Converters with Operational Amplifiers

TFT-LCD DC-DC Converters with
Operational Amplifiers
Undervoltage Lockout (UVLO)
The undervoltage-lockout (UVLO) circuit compares the
input voltage at IN with the UVLO threshold (2.5V rising,
2.35V falling, typ) to ensure the input voltage is high
enough for reliable operation. The 150mV (typ) hysteresis
prevents supply transients from causing a restart. Once
the input voltage exceeds the UVLO rising threshold,
startup begins. When the input voltage falls below the
UVLO falling threshold, the controller turns off the main
step-up regulator, turns off the linear-regulator outputs,
and disables the switch control block; the operational-
amplifier outputs are high impedance.
Reference Voltage (REF)
The reference output is nominally 1.25V and can
source at least 50µA (see the Typical Operating
Characteristics). Bypass REF with a 0.22µF ceramic
capacitor connected between REF and AGND.
Power-Up Sequence and Soft-Start
Once the voltage on IN exceeds approximately 1.7V,
the reference turns on. With a 0.22µF REF bypass
capacitor, the reference reaches its regulation voltage
of 1.25V in approximately 1ms. When the reference
voltage exceeds 1.0V, the ICs enable the main step-up
regulator, the gate-on linear-regulator controller, and
the gate-off linear-regulator controller simultaneously.
The IC employs soft-start for each regulator to minimize
inrush current and voltage overshoot and to ensure a
well-defined startup behavior. During the soft-start, the
main step-up regulator directly limits the peak inductor
current. The current-limit level is increased through the
soft-start period from 0 up to the full current-limit value
in eight equal current steps (ILIM / 8). The maximum
load current is available after the output voltage reach-
es regulation (which terminates soft-start), or after the
soft-start timer expires. Both linear-regulator controllers
use a 7-bit soft-start DAC. For the gate-on linear regula-
tor, the DAC output is stepped in 128 steps from zero
up to the reference voltage. For the gate-off linear regu-
lator, the DAC output steps from the reference down to
250mV in 128 steps. The soft-start duration is 14ms
(typ) for all three regulators.
A capacitor (C_DEL) from DEL to AGND determines the
switch-control-block startup delay. After the input volt-
age exceeds the UVLO threshold (2.5V typ) and the
soft-start routine for each regulator is complete and
there is no fault detected, a 5µA current source starts
charging C_DEL. Once the capacitor voltage exceeds
2.5V
1.05V
V_IN
V_REF
V_MAIN
V_GON
12ms
1.25V
V_GOFF
V_DEL
INPUT SOFT- SOFT-
VOLTAGE START START
OK BEGINS ENDS
SWITCH
CONTROL
ENABLED
Figure 6. Power-Up Sequence
1.25V (typ), the switch-control block is enabled as
shown in Figure 6. After the switch-control block is
enabled, COM can be connected to SRC or DRN
through the internal p-channel switches, depending
upon the state of CTL. Before startup and when IN is
less than V_UVLO, DEL is internally connected to AGND
to discharge C_DEL. Select C_DEL to set the delay time
using the following equation:
C_DEL
=
DELAY
_
TIME
×
5µA
1.25V
Switch-Control Block
The switch-control input (CTL) is not activated until all
four of the following conditions are satisfied: the input
voltage exceeds V_UVLO, the soft-start routine of all the
regulators is complete, there is no fault condition
detected, and V_DEL exceeds its turn-on threshold. As
shown in Figure 7, COM is pulled down to PGND
through a 1kΩ resistor when the switch control is not
activated. Once activated and if CTL is high, the 5Ω
internal p-channel switch (Q1) between COM and SRC
turns on and the 30Ω p-channel switch (Q2) between
DRN and COM turns off. If CTL is low, Q1 turns off and
Q2 turns on.
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