DS1972_10 Datasheet, PDF (17/23 Pages) Maxim Integrated Products – 1024-Bit EEPROM iButton

1024-Bit EEPROM iButton
V_PUP
V_IHMASTER
V_TH
V_TL
V_ILMAX
0V
MASTER Tx "RESET PULSE"
t_RSTL
t_F
RESISTOR
MASTER Rx "PRESENCE PULSE"
ε
t_MSP
t_PDH
MASTER
t_PDL
t_RSTH
t_REC
DS1972
Figure 10. Initialization Procedure: Reset and Presence Pulse
Read/Write Time Slots
Data communication with the DS1972 takes place in
time slots that carry a single bit each. Write time slots
transport data from bus master to slave. Read time
slots transfer data from slave to master. Figure 11 illus-
trates the definitions of the write and read time slots.
All communication begins with the master pulling the
data line low. As the voltage on the 1-Wire line falls
below the threshold V_TL, the DS1972 starts its internal
timing generator that determines when the data line is
sampled during a write time slot and how long data is
valid during a read time slot.
Master-to-Slave
For a write-one time slot, the voltage on the data line
must have crossed the V_TH threshold before the write-
one low time t_W1LMAX is expired. For a write-zero time
slot, the voltage on the data line must stay below the
V_TH threshold until the write-zero low time t_W0LMIN is
expired. For the most reliable communication, the volt-
age on the data line should not exceed V_ILMAX during
the entire t_W0L or t_W1L window. After the V_TH threshold
has been crossed, the DS1972 needs a recovery time
t_REC before it is ready for the next time slot.
Slave-to-Master
A read-data time slot begins like a write-one time slot.
The voltage on the data line must remain below V_TL
until the read low time t_RL is expired. During the t_RL
window, when responding with a 0, the DS1972 starts
pulling the data line low; its internal timing generator
determines when this pulldown ends and the voltage
starts rising again. When responding with a 1, the
DS1972 does not hold the data line low at all, and the
voltage starts rising as soon as t_RL is over.
The sum of t_RL + δ (rise time) on one side and the inter-
nal timing generator of the DS1972 on the other side
define the master sampling window (t_MSRMIN to
t_MSRMAX), in which the master must perform a read
from the data line. For the most reliable communication,
t_RL should be as short as permissible, and the master
should read close to but no later than t_MSRMAX. After
reading from the data line, the master must wait until
t_SLOT is expired. This guarantees sufficient recovery
time t_REC for the DS1972 to get ready for the next time
slot. Note that t_REC specified herein applies only to a
single DS1972 attached to a 1-Wire line. For multide-
vice configurations, t_REC must be extended to accom-
modate the additional 1-Wire device input capacitance.
Alternatively, an interface that performs active pullup
during the 1-Wire recovery time such as the DS2482-
x00 or DS2480B 1-Wire line drivers can be used.
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