DS1825 Datasheet, PDF (17/21 Pages) Maxim Integrated Products – Programmable Resolution 1-Wire Digital Thermometer With 4-Bit ID

DS1825 Programmable Resolution 1-Wire Digital Thermometer With 4-Bit ID
Figure 15. READ/WRITE TIME SLOT TIMING DIAGRAM
START
OF SLOT
MASTER WRITE “0” SLOT
VPU
1-WIRE BUS
GND
60 ms < TX “0” < 120 ms
DS1825 Samples
MIN
TYP
MAX
15 ms
15 ms
30 ms
START
OF SLOT
MASTER WRITE “1” SLOT
Â¥ 1 ms < TREC <
> 1 ms
15 ms
DS1825 Samples
MIN
TYP
MAX
15 ms
30 ms
VPU
1-WIRE BUS
GND
> 1 ms
MASTER READ “0” SLOT
15 ms
Master samples
45 ms
> 1 ms
MASTER READ “1” SLOT
Â¥ 1 ms < TREC <
15 ms
Master samples
LINE TYPE LEGEND
Bus master pulling low
Resistor pullup
DS1825 pulling low
READ TIME SLOTS
The DS1825 can only transmit data to the master when the master issues read time slots. Therefore, the master
must generate read time slots immediately after issuing a Read Scratchpad [BEh] or Read Power Supply [B4h]
command, so that the DS1825 can provide the requested data. In addition, the master can generate read time slots
after issuing Convert T [44h] or Recall E² [B8h] commands to find out the status of the operation as explained in
the DS1825 FUNCTION COMMAND section.
All read time slots must be a minimum of 60ms in duration with a minimum of a 1ms recovery time between slots. A
read time slot is initiated by the master device pulling the 1-Wire bus low for a minimum of 1ms and then releasing
the bus (see Figure 14). After the master initiates the read time slot, the DS1825 will begin transmitting a 1 or 0 on
bus. The DS1825 transmits a 1 by leaving the bus high and transmits a 0 by pulling the bus low. When transmitting
a 0, the DS1825 will release the bus by the end of the time slot, and the bus will be pulled back to its high idle state
by the pullup resister. Output data from the DS1825 is valid for 15ms after the falling edge that initiated the read
time slot. Therefore, the master must release the bus and then sample the bus state within 15ms from the start of
the slot.
Figure 15 illustrates that the sum of T_INIT, T_RC, and T_SAMPLE must be less than 15ms for a read time slot. Figure 16
shows that system timing margin is maximized by keeping T_INIT and T_RC as short as possible and by locating the
master sample time during read time slots towards the end of the 15ms period.
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