MAX77801 Datasheet, PDF (16/25 Pages) Maxim Integrated Products – Flexibility Supports Various Designs

MAX77801
High-Efficiency Buck-Boost Regulator
Writing Multiple Bytes Using
Register-Data Pairs
The figure below shows the protocol for I²C master device
to write multiple bytes to the MAX77801 using register-
data pairs. This protocol allows I²C master device to
address the slave only once and then send data to mul-
tiple registers in a random order. Registers can be written
continuously until the master issues a STOP condition.
The multiple byte register-data pair protocol is as follows:
1. The master sends a START command.
2. The master sends the 7-bit slave address followed by
a write bit.
3. The addressed slave asserts an ACKNOWLEDGE by
pulling SDA low.
4. The master sends an 8-bit register pointer.
5. The slave acknowledges the register pointer.
6. The master sends a data byte.
7. The slave acknowledges the data byte. The next ris-
ing edge on SDA loads the data byte into its target
register and the data becomes active.
8. Steps 5 to 7 are repeated as many times as the mas-
ter requires.
The master sends a STOP condition. During the rising
edge of the stop related SDA edge, the data byte that
was previously written is loaded into the target register
and becomes active.
Reading from a Single Register
I²C master device reads one byte of data to the MAX77801.
This protocol is the same as SMBus specification’s read
byte protocol.
The read byte protocol is as follows:
1. The master sends a START command.
2. The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
3. The addressed slave asserts an ACKNOWLEDGE by
pulling SDA low.
4. The master sends an 8-bit register pointer.
5. The slave acknowledges the register pointer.
6. The master sends a REPEATED START command.
7. The master sends the 7-bit slave address followed by
a read bit (R/W = 1).
8. The addressed slave asserts an ACKNOWLEDGE by
pulling SDA low.
9. The addressed slave places 8 bits of data on the bus
from the location specified by the register pointer.
10. The master issues a NOT-ACKNOWLEDGE.
11. The master sends a STOP condition or a REPEATED
START condition. Issuing a STOP ensures that the
bus input filters are set for 1MHz or slower operation.
Issuing a REPEATED START leaves the bus input
filters in their current state.
MASTER TO
SLAVE
LEGEND
SLAVE TO
MASTER
1
7
S SLAVE ADDRESS
11
8
1
0 A REGISTER POINTER A
R/nW
8
DATA
SDA
B1
B0
A
ACKNOWLEDGE
SCL
7
8
9
1
1
A OR nA P OR Sr*
NUMBER OF BITS
THE DATA IS LOADED INTO
THE TARGET REGISTER AND
BECOMES ACTIVE DURING
THIS RISING EDGE.
*P FORCES THE BUS FILTERS TO SWITCH
TO THEIR ≤ 1MHZ MODE. Sr LEAVES THE
BUS FILTERS IN THEIR CURRENT STATE.
Figure 12. Writing to Multiple Registers with Multiple Byte Register-Data Pairs Protocol
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