MAX3421E Datasheet, PDF (16/29 Pages) Maxim Integrated Products – USB Peripheral/Host Controller with SPI Interface

USB Peripheral/Host Controller
with SPI Interface
help sustain bandwidth by allowing data to move concur-
rently over USB and the SPI interface.
V_CC
Power the USB transceiver and digital logic by apply-
ing a positive 3.3V supply to V_CC. Bypass V_CC to GND
with a 1.0µF ceramic capacitor as close to the V_CC pin
as possible.
V_L
V_L acts as a reference level for the SPI interface and all
other digital inputs and outputs. Connect V_L to the sys-
tem’s logic-level power supply. Internal level translators
and V_L allow the SPI interface and all general-purpose
inputs and outputs to operate at a system voltage
between 1.4V and 3.6V.
VBCOMP
The MAX3421E features a USB V_BUS detector input,
VBCOMP. The VBCOMP pin can withstand input volt-
ages up to 6V. Bypass VBCOMP to GND with a 1.0µF
ceramic capacitor. VBCOMP is internally connected to
a voltage comparator to allow the SPI master to detect
(through an interrupt or checking a register bit) the
presence or loss of power on V_BUS. VBCOMP does not
power any internal circuitry inside the MAX3421E.
VBCOMP is pulled down to ground with R_IN (see
Electrical Characteristics).
VBCOMP in Peripheral Mode
VBCOMP is internally connected to a voltage compara-
tor so that the SPI master can detect the presence or
absence of V_BUS. According to the USB 2.0 specifica-
tion, a self-powered peripheral must disconnect its
1.5kΩ pullup resistor to D+ in the event that the host
turns off bus power. The VBGATE bit in the USBCTL
(R15) register provides the option for the MAX3421E
internal logic to automatically disconnect the 1.5kΩ
resistor on D+. The VBGATE and CONNECT bits of
USBCTL (R15), along with the VBCOMP comparator
output (VBUS_DET), control the pullup resistor between
V_CC and D+ as shown in Table 3 and the Functional
Diagram. Note that if VBGATE = 1 and VBUS_DET = 0,
the pullup resistor is disconnected regardless of the
CONNECT bit setting. If the device using the
MAX3421E is bus powered (through a +3.3V regulator
connected to V_CC), the MAX3421E VBCOMP input can
be used as a general-purpose input. See the
Applications Information section for more details about
this connection.
Table 3. Internal Pullup Resistor Control
in Peripheral Mode
CONNECT
0
1
1
1
VBGATE
X
0
1
1
VBUS_DET
X
X
0
1
PULLUP
Not Connected
Connected
Not Connected
Connected
VBCOMP in Host Mode
When using the MAX3421E in host mode, the presence
of VBUS does not need to be detected. In this case, the
VBCOMP input can be used as a general-purpose
input.
D+ and D-
The internal USB full-/low-speed transceiver is brought
out to the bidirectional data pins D+ and D-. These pins
are ±15kV ESD protected. Connect D+ and D- to a
USB B connector through 33Ω ±1% series resistors.
D+ and D- in Peripheral Mode
In peripheral mode, the D+ and D- pins connect to a
USB B connector through series resistors. A switchable
1.5kΩ pullup resistor is internally connected to D+.
D+ and D- in Host Mode
In host mode, the D+ and D- pins connect to a USB A
connector through series resistors. Switchable 15kΩ
pulldown resistors are internally connected to D+ and
D-. The DPPULLDN and DMPULLDN bits in the MODE
(R27) register control the connection between D+ and
D- to GND. For host operation, set these bits to 1 to
enable the pulldown resistors. A host interrupt bit called
CONNIRQ alerts the SPI master when a peripheral is
attached or detached.
XI and XO
XI and XO connect an external 12MHz crystal to the
internal oscillator circuit. XI is the crystal oscillator
input, and XO is the crystal oscillator output. Connect
one side of a 12MHz ±0.25% parallel resonant crystal
to XI, and connect XO to the other side. Connect load
capacitors (20pF max) to ground on both XI and XO. XI
can also be driven with an external 12MHz ±0.25%
clock. If driving XI with an external clock, leave XO
unconnected. The external clock must meet the voltage
characteristics depicted in the Electrical Character-
istics table. Internal logic is single-edge triggered. The
external clock should have a nominal 50% duty cycle.
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