MAX16809 Datasheet, PDF (16/23 Pages) Maxim Integrated Products – Integrated 16-Channel LED Drivers with Switch-Mode Boost and SEPIC Controller

Integrated 16-Channel LED Drivers with
Switch-Mode Boost and SEPIC Controller
LED Driver
4-Wire Interface
The MAX16809/MAX16810 also operate in a stand-
alone mode (see the Typical Operating Circuits). For
use with a microcontroller, the MAX16809/MAX16810
feature a 4-wire serial interface using DIN, CLK, LE, OE
inputs and DOUT as a data output. This interface is
used to write the LED channels’ data to the MAX16809/
MAX16810. The serial-interface data word length is 16
bits, D0–D15. See Figure 3.
The functions of the five interface pins are as follows:
DIN is the serial-data input, and must be stable when it
is sampled on the rising edge of CLK. Data is shifted in
MSB first. This means that data bit D15 is clocked in
first, followed by 15 more data bits, finishing with the
LSB, D0.
CLK is the serial-clock input that shifts data at DIN into
the MAX16809/MAX16810’s 16-bit shift register on its
rising edge.
LE is the latch-enable input of the MAX16809/MAX16810
that transfers data from the 16-bit shift register to its 16-
bit output latches (transparent latch). The data latches
on the falling edge of LE (Figure 4). The fourth input (OE)
provides output-enable control of the output drivers.
When OE is driven high, the outputs (OUT0–OUT15) are
forced to high impedance without altering the contents of
the output latches. Driving OE low enables the outputs to
follow the state of the output latches. OE is independent
of the serial interface operation. Data can be shifted into
the serial-interface shift register and latched, regardless
of the state of OE. DOUT is the serial-data output that
shifts data out from the MAX16809/MAX16810’s 16-bit
shift register on the rising edge of CLK. Data at DIN
propagates through the shift register and appears at
DOUT 16 clock cycles later. Table 1 shows the 4-wire
serial-interface truth table.
Table 1. 4-Wire Serial-Interface Truth Table
SERIAL
DATA
CLOCK
INPUT
SHIFT REGISTER
CONTENTS
LOAD
INPUT
INPUT
DIN ^{CLK D0 D1 D2 … Dn-1 Dn LE}
LATCH CONTENTS
D0 D1 D2 … Dn-1 Dn
BLANKING
INPUT
OE
OUTPUT CONTENTS
CURRENT AT OUT_ _
D0 D1 D2 … Dn-1 Dn
H
H R0 R1 … Rn-2 Rn-1
L
L R0 R1 … Rn-2 Rn-1
X
R0 R1 R2 … Rn-1 Rn
X X X… X X
L R0 R1 R2 … Rn-1 Rn
P0 P1 P2 … Pn-1 Pn
H P0 P1 P2 … Pn-1 Pn
L
P0 P1 P2 … Pn-1 Pn
X X X… X X
H
L L L… L L
L = Low Logic Level
H = High Logic Level
X = Don’t Care
P = Present State (Shift Register)
R = Previous State (Latched)
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