DS28CZ04 Datasheet, PDF (16/22 Pages) Maxim Integrated Products – 4kbit I²C/SMBus EEPROM with Nonvolatile PIO

DS28CZ04: 4kbit I²C/SMBus EEPROM with Nonvolatile PIO
Figure 7. SRAM and PIO Writing
Memory Location
Address
Function
00h to 77h
Memory
78h
Reserved
79h
Reserved
7Ah
Register
7Bh
Register
7Ch
PIO R/W
7Dh
PIO R/W
7Eh
PIO R/W
7Fh
PIO R/W
80h to FFh
Memory
PIO Multi-Address Mode
SRAM Write PIO Direct
PIO Single-Address Mode
SRAM Write PIO Direct
00h to FFh
Memory
When writing to a PIO, as shown in Figure 8, any state change is triggered by the SCL pulse that the master
generates for the acknowledge bit of byte written to the PIO Read/Write Access Register. After the output transition
time t_PV is expired, the state change is completed. In PIO Single-Address mode all PIOs change their state
approximately at the same time; in this mode the fastest rate for a PIO to change its state is f_SCL/9. In PIO Multi-
Address Mode each PIO is accessed individually; in this mode when writing in an endless loop the fastest rate for a
PIO to change its state is f_SCL/36. Transfer of data can be stopped at any moment by a STOP condition. When this
occurs, data present at the last acknowledged phase is valid.
Figure 8. PIO Write Access Timing
SRAM Write
SDA
MSB (7Bh) data
LSB A MSB
SCL
PIO
DATA1
LSB A MSB
tPV
DATA2
LSB A MSB
DATA1
DATA3
LSB A
DATA2
PIO Direct
SDA S A6 A5 A4 A3 A2 A1 P0 0 A MSB
PIO Address
LSB A MSB
SCL
PIO
DATA1
LSB A MSB
tPV
DATA2
LSB A
DATA1
Reading Memory and PIOs
If the DS28CZ04 is addressed in read access mode, the read pointer determines the location from which the
master will start reading. The read pointer is set when the DS28CZ04 is accessed in write access mode, either for
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