MAX5713 Datasheet, PDF(15/27 Page) Maxim Integrated Products – Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and SPI Interface

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MAX5713 Datasheet, PDF (15/27 Pages) Maxim Integrated Products – Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and SPI Interface

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MAX5713/MAX5714/MAX5715

Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered

Output DACs with Internal Reference and SPI Interface

Detailed Description

The MAX5713/MAX5714/MAX5715 are 4-channel, low-

power, 8-/10-/12-bit buffered voltage-output DACs. The

2.7V to 5.5V wide supply voltage range and low-power

consumption accommodates most low-power and low-

voltage applications. The devices present a 100kI load

to the external reference. The internal output buffers

allow rail-to-rail operation. An internal voltage reference

is available with software selectable options of 2.048V,

2.5V, or 4.096V. The devices feature a 50MHz, 3-wire

SPI/QSPI/MICROWIRE/DSP-compatible serial interface to

save board space and reduce the complexity in isolated

applications. The MAX5713/MAX5714/MAX5715 include

a serial-in/parallel-out shift register, internal CODE and

DAC registers, a power-on-reset (POR) circuit to initialize

the DAC outputs to code zero, and control logic. CLR is

available to asynchronously clear the device indepen-

dent of the serial interface.

DAC Outputs (OUT_)

The MAX5713/MAX5714/MAX5715 include internal buf-

fers on all DAC outputs. The internal output buffers

provide improved load regulation for the DAC outputs.

The output buffers slew at 1V/Fs (typ) and drive resistive

loads as low as 2kI in parallel with as much as 500pF

of capacitance.. The analog supply voltage (VDD) deter-

mines the maximum output voltage range of the devices

as VDD powers the output buffer. Under no-load condi-

tions, the output buffers drive from GND to VDD, subject

to offset and gain errors. With a 2kÏ load to GND, the

output buffers drive from GND to within 200mV of VDD.

With a 2kÏ load to VDD, the output buffers drive from VDD

to within 200mV of GND.

The DAC ideal output voltage is defined by:

V= OUT

VREF

where D = code loaded into the DAC register, VREF =

reference voltage, N = resolution.

Internal Register Structure

The user interface is separated from the DAC logic to

minimize digital feedthrough. Within the serial interface

is an input shift register, the contents of which can be

routed to control registers, individual, or multiple DACs

as determined by the user command.

Within each DAC channel there is a CODE register

followed by a DAC latch register (see the Detailed

Functional Diagram). The contents of the CODE register

hold pending DAC output settings which can later be

loaded into the DAC registers. The CODE register can be

updated using both CODE and CODE_LOAD user com-

mands. The contents of the DAC register hold the current

DAC output settings. The DAC register can be updated

directly from the serial interface using the CODE_LOAD

commands or can upload the current contents of the

CODE register using LOAD commands or the LDAC

hardware pin.

The contents of both CODE and DAC registers are main-

tained during power-down states, so that when the DACs

are powered on, they return to their previously stored

output settings. Any CODE or LOAD commands issued

during power-down states continue to update the register

contents. SW_CLEAR and SW_RESET commands reset

the contents of all CODE and DAC registers to their zero-

scale defaults.

Internal Reference

The MAX5713/MAX5714/MAX5715 include an internal

precision voltage reference that is software selectable

to be 2.048V, 2.500V, or 4.096V. When an internal refer-

ence is selected, that voltage is available on the REF

pin for other external circuitry (see the Typical Operating

Circuits) and can drive a 25kI load.

External Reference

The external reference input has a typical input

impedance of 100kI and accepts an input voltage

from +1.24V to VDD. Connect an external voltage

supply between REF and GND to apply an exter-

nal reference. The MAX5713/MAX5714/MAX5715

power up and reset to external reference mode. Visit

www.maxim-ic.com/products/references for a list of

available external voltage-reference devices.

Load DAC (LDAC) Input

(TSSOP Package Only)

The MAX5713/MAX5714/MAX5715 feature an active-

low LDAC logic input that allows the outputs to update

asynchronously. Connect LDAC to VDDIO or keep LDAC

high during normal operation when the device is con-

trolled only through the serial interface. Drive LDAC low

to simultaneously update the DAC outputs with data

from the CODE registers. Holding LDAC low causes the

DAC registers to become transparent and CODE data is

passed through to the DAC registers immediately updat-

ing the DAC outputs. A software CONFIG command can

be used to configure the LDAC operation of each DAC

independently.

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