MAX4548 Datasheet, PDF (15/20 Pages) Maxim Integrated Products – Serially Controlled, Triple 3x2 Audio/Video Crosspoint Switches

Serially Controlled, Triple 3x2 Audio/Video
Crosspoint Switches
CS
SCLK
DIN
1
24
C7
C0 D15
D0
COMMAND BYTE
DATA BYTE
Figure 6. 3-Wire Serial-Interface Communication
CS
•••
SCLK
DIN
DOUT
t_CSS
t_CSH
t_DS
t_DH
t_DV
t_CH
t_CL
•••
•••
•••
t_CSH
t_DO
t_TR
Figure 7. 3-Wire Serial-Interface Timing Details
the same configuration. Any block that is not selected
in the command byte remains unchanged.
2-Wire Serial Interface
The MAX4548 uses a 2-wire I²C-compatible serial inter-
face. The COM_ _ registers and the Clickless Mode
register use the “WriteByte” protocol, which consists of
an address byte, followed by a command byte, fol-
lowed by a data byte (Table 5). The Bias register uses
the “WriteWord” protocol, which consists of an address
byte, followed by a command byte, followed by a data
word (Table 6).
To address a given chip, the A0 and A1 bits in the
address byte must duplicate the values present at the
A0 and A1 pins of that chip. The rest of the address bits
must match those shown in Tables 5 and 6. The com-
mand and data-byte details are described in the
Command-Byte and Data-Byte Programming section.
The 2-wire serial interface requires only two I/O lines of
a standard microprocessor port. Figures 3, 4, and 5
detail the timing diagram for signals on the 2-wire bus,
while Tables 5 and 6 detail the format of the signals.
The MAX4548 is a receive-only device and must be
controlled by the bus master device. A bus master
device communicates by transmitting the address byte
of the slave device over the bus and then transmitting
the desired information. Each transmission consists of
a start condition, a command byte, a data byte or word,
and finally a stop condition. The slave device acknowl-
edges the recognition of its address by pulling the SDA
line low for one clock period after the address byte is
transmitted. The slave device also issues a similar
acknowledgment after the command byte and again
after each data byte.
Start and Stop Conditions
The bus master signals the beginning of a transmission
with a start condition by transitioning SDA from high to
low while SCL is high. When the master has finished
communicating with the slave, it issues a stop condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.
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