MAX3070E Datasheet, PDF (15/25 Pages) Maxim Integrated Products – +3.3V, ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers

+3.3V, ±15kV ESD-Protected, Fail-Safe,
Hot-Swap, RS-485/RS-422 Transceivers
Detailed Description
The MAX3070E–MAX3079E high-speed transceivers for
RS-485/RS-422 communication contain one driver and
one receiver. These devices feature fail-safe circuitry,
which guarantees a logic-high receiver output when the
receiver inputs are open or shorted, or when they are
connected to a terminated transmission line with all dri-
vers disabled (see the Fail-Safe section). The
MAX3070E/MAX3072E/MAX3073E/MAX3075E/
MAX3076E/MAX3078E/MAX3079E also feature a hot-
swap capability allowing line insertion without erro-
neous data transfer (see the Hot Swap Capability
section). The MAX3070E/MAX3071E/MAX3072E feature
reduced slew-rate drivers that minimize EMI and
reduce reflections caused by improperly terminated
cables, allowing error-free data transmission up to
250kbps. The MAX3073E/MAX3074E/MAX3075E also
offer slew-rate limits allowing transmit speeds up to
500kbps. The MAX3076E/MAX3077E/MAX3078Es’ dri-
ver slew rates are not limited, making transmit speeds
up to 16Mbps possible. The MAX3079E’s slew rate is
selectable between 250kbps, 500kbps, and 16Mbps
by driving a selector pin with a three-state driver.
The MAX3072E/MAX3075E/MAX3078E are half-duplex
transceivers, while the MAX3070E/MAX3071E/
MAX3073E/MAX3074E/MAX3076E/MAX3077E are full-
duplex transceivers. The MAX3079E is selectable
between half- and full-duplex communication by driving
a selector pin (SRL) high or low, respectively.
All devices operate from a single 3.3V supply. Drivers are
output short-circuit current limited. Thermal-shutdown cir-
cuitry protects drivers against excessive power dissipa-
tion. When activated, the thermal-shutdown circuitry
places the driver outputs into a high-impedance state.
Receiver Input Filtering
The receivers of the MAX3070E–MAX3075E, and the
MAX3079E when operating in 250kbps or 500kbps
mode, incorporate input filtering in addition to input
hysteresis. This filtering enhances noise immunity with
differential signals that have very slow rise and fall
times. Receiver propagation delay increases by 25%
due to this filtering.
Fail-Safe
The MAX3070E family guarantees a logic-high receiver
output when the receiver inputs are shorted or open, or
when they are connected to a terminated transmission
line with all drivers disabled. This is done by setting the
receiver input threshold between -50mV and -200mV. If
the differential receiver input voltage (A - B) is greater
than or equal to -50mV, RO is logic high. If A - B is less
than or equal to -200mV, RO is logic low. In the case of
a terminated bus with all transmitters disabled, the
receiver’s differential input voltage is pulled to 0V by
the termination. With the receiver thresholds of the
MAX3070E family, this results in a logic high with a
50mV minimum noise margin. Unlike previous fail-safe
devices, the -50mV to -200mV threshold complies with
the ±200mV EIA/TIA-485 standard.
Hot-Swap Capability
(Except MAX3071E/MAX3074E/MAX3077E)
Hot-Swap Inputs
When circuit boards are inserted into a hot, or pow-
ered, backplane, differential disturbances to the data
bus can lead to data errors. Upon initial circuit board
insertion, the data communication processor under-
goes its own power-up sequence. During this period,
the processor’s logic-output drivers are high imped-
ance and are unable to drive the DE and RE inputs of
these devices to a defined logic level. Leakage cur-
rents up to ±10µA from the high-impedance state of the
processor’s logic drivers could cause standard CMOS
enable inputs of a transceiver to drift to an incorrect
logic level. Additionally, parasitic circuit board capaci-
tance could cause coupling of V_CC or GND to the
enable inputs. Without the hot-swap capability, these
factors could improperly enable the transceiver’s driver
or receiver.
When V_CC rises, an internal pulldown circuit holds DE
low and RE high. After the initial power-up sequence,
the pulldown circuit becomes transparent, resetting the
hot-swap tolerable input.
Hot-Swap Input Circuitry
The enable inputs feature hot-swap capability. At the
input there are two NMOS devices, M1 and M2
(Figure 9). When V_CC ramps from zero, an internal 10µs
timer turns on M2 and sets the SR latch, which also
turns on M1. Transistors M2, a 500µA current sink, and
M1, a 100µA current sink, pull DE to GND through a
5kΩ resistor. M2 is designed to pull DE to the disabled
state against an external parasitic capacitance up to
100pF that can drive DE high. After 10µs, the timer
deactivates M2 while M1 remains on, holding DE low
against three-state leakages that can drive DE high. M1
remains on until an external source overcomes the
required input current. At this time, the SR latch resets
and M1 turns off. When M1 turns off, DE reverts to a
standard, high-impedance CMOS input. Whenever V_CC
drops below 1V, the hot-swap input is reset.
For RE there is a complementary circuit employing two
PMOS devices pulling RE to V_CC.
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