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MAX2066ETL Datasheet, PDF (15/23 Pages) Maxim Integrated Products – 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA
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50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
PIN
1, 16, 19, 22,
24–28, 30,
31, 33–36
2, 3, 32,
37–40
4
5
6
7
8
9
10
11
12
13
14
15
17
18
20
21
23
29
—
NAME
GND
GND
DATA
CLK
CS
VDD_LOGIC
SER/PAR
STATE_A
STATE_B
D4
D3
D2
D1
D0
AMP_OUT
RSET
AMP_IN
VCC_AMP
ATTEN_OUT
ATTEN_IN
EP
Ground
DESCRIPTION
Pin Description
Ground. See the Pin-Compatibility Considerations section.
SPI Data Digital Input
SPI Clock Digital Input
SPI Chip-Select Digital Input
Digital Logic Supply Input. Connect to the digital logic power supply, VDD. Bypass to GND with a
10nF capacitor as close as possible to the pin.
Digital Attenuator SPI or Parallel Control Selection Logic Input. Logic 0 = parallel control,
Logic 1 = serial control.
Digital Attenuator Preprogrammed Attenuation State Logic Input
State A
State B
Digital Attenuator
Logic = 0
Logic = 0
Preprogrammed State 1
Logic = 1
Logic = 0
Preprogrammed State 2
Logic = 0
Logic = 1
Preprogrammed State 3
Logic = 1
Logic = 1
Preprogrammed State 4
16dB Attenuator Logic Input. Logic 0 = disable, Logic 1 = enable.
8dB Attenuator Logic Input. Logic 0 = disable, Logic 1 = enable.
4dB Attenuator Logic Input. Logic 0 = disable, Logic 1 = enable.
2dB Attenuator Logic Input. Logic 0 = disable, Logic 1 = enable.
1dB Attenuator Logic Input. Logic 0 = disable, Logic 1 = enable.
Driver Amplifier Output (50Ω). See the Typical Application Circuit for details.
Driver Amplifier Bias Setting. See the External Bias section.
Driver Amplifier Input (50Ω). See the Typical Application Circuit for details.
Driver Amplifier Supply Voltage Input. Connect to the VCC power supply. Bypass to GND with
1000pF and 10nF capacitors as close as possible to the pin with the smaller value capacitor
closer to the part.
5-Bit Digital Attenuator Output (50Ω). Internally matched to 50Ω. Requires an external DC
blocking capacitor.
5-Bit Digital Attenuator Input (50Ω). Internally matched to 50Ω. Requires an external DC blocking
capacitor.
Exposed Pad. Internally connected to GND. Connect EP to GND for proper RF performance and
enhanced thermal dissipation.
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