MAX2009 Datasheet, PDF (15/19 Pages) Maxim Integrated Products – 1200MHz to 2500MHz Adjustable RF Predistorter

1200MHz to 2500MHz Adjustable
RF Predistorter
Gain Expansion Breakpoint
The gain expansion breakpoint is usually controlled by a
DAC connected through the GBP pin. The GBP input
voltage range of 0.5V to 5V corresponds to a breakpoint
input power range of 3dBm to 23dBm. To achieve the
optimal performance, the gain expansion breakpoint of
the MAX2009 must be set to equal the gain compres-
sion point of the PA. The GBP control has a minimal
effect on the small-signal gain when operated from 0.5V
to 5V.
Gain Expansion Slope
In addition to properly setting the breakpoint, the gain
expansion slope of the MAX2009 must also be adjusted
to compensate for the PA’s gain compression. The
slope should be set using the following equation:
MAX2009 _ SLOPE = ^{−PA _ SLOPE}
1+ PA _ SLOPE
where:
MAX2009_SLOPE = MAX2009 gain section’s slope in
dB/dB.
PA_SLOPE = PA’s gain slope in dB/dB, a negative
number for compressive behavior.
To modify the gain expansion slope, two adjustments
must be made to the biases applied on pins GCS and
GFS. Both GCS and GFS have an input voltage range of
0V to V_CC, corresponding to a slope of approximately
0.1dB/dB to 0.6dB/dB. The slope is set to maximum
when V_GCS = 0V and V_GFS = +5V, and the slope is at its
minimum when V_GCS = +5V and V_GFS = 0V.
Unlike the GBP pin, modifying the gain expansion slope
bias on the GCS pin causes a change in the part’s inser-
tion loss and noise figure. For example, a smaller slope
caused by GCS results in a better insertion loss and
lower noise figure. The GFS does not affect the insertion
loss. It can provide up to -30% or +30% total slope varia-
tion around the nominal slope set by GCS.
Large amounts of GCS bias adjustment can also lead to
an undesired (or residual) phase expansion/compres-
sion behavior. There exists an optimal bias voltage that
minimizes this parasitic behavior (typically GCS = 1.0V).
Control voltages higher than the optimal result in para-
sitic phase expansion, lower control voltages result in
phase compression. GFS does not contribute to the
phase behavior and is preferred for slope control.
Applications Information
The following section describes the tuning methodology
best implemented with a class A amplifier. Other classes
of operation may require significantly different settings.
Gain and Phase Expansion Optimization
The best approach to improve the ACPR of a PA is to
first optimize the AM-PM response of the phase sec-
tion. For most high-frequency LDMOS amplifiers,
improving the AM-PM response provides the bulk of the
ACPR improvement. Figure 4 shows a typical configu-
ration of the phase tuning circuit. A power sweep on a
network analyzer allows quick real-time tuning of the
AM-PM response. First, tune PBIN to achieve the phase
expansion starting point (breakpoint) at the same point
where the PA’s phase compression begins. Next, use
control pins PF_S1, PDCS1, and PDCS2 to obtain the
optimal AM-PM response. The typical values for these
pins are shown in Figure 4.
To further improve the ACPR, connect the phase out-
put to the gain input through a preamplifier. The pre-
amplifier is used to compensate for the high insertion
loss of the gain section. Figure 5 shows a typical appli-
cation circuit of the MAX2009 with the phase section
cascaded to the gain section for further ACPR opti-
mization. Similar to tuning the phase section, first tune
the gain expansion breakpoint through the GBP pin
and adjust for the desired gain expansion with pins
GCS and GFS. To minimize the effect of GCS on the
parasitic phase response, minimize the control voltage
to around 1V. Some retuning of the AM-PM response
may be necessary.
Layout Considerations
A properly designed PC board is an essential part of
any high-frequency circuit. To minimize external com-
ponents, the PC board can be designed to incorporate
small values of inductance and capacitance to optimize
the input and output VSWR (refer to the MAX2009). The
phase section’s PFS1 and PFS2 pins are sensitive to
external parasitics. Minimize trace lengths and keep
varactor diodes close to the pins. Remove the ground
plane underneath the traces can further help reduce
the parasitic capacitance. For best performance, route
the ground pin traces directly to the grounded EP
underneath the package. Solder the EP on the bottom
of the device package evenly to the board ground
plane to provide a heat transfer path along with signal
grounding.
______________________________________________________________________________________ 15