MAX15062 Datasheet, PDF (15/23 Pages) Maxim Integrated Products – Step-Down DC-DC Converters

MAX15062
60V, 300mA, Ultra-Small, High-Efficiency,
Synchronous Step-Down DC-DC Converters
Detailed Description
The MAX15062 high-efficiency, high-voltage, syn-
chronous step-down DC-DC converter with integrated
MOSFETs operates over a wide 4.5V to 60V input voltage
range. The converter delivers output current up to 300mA
at 3.3V (MAX15062A), 5V (MAX15062B), and adjustable
output voltages (MAX15062C). When EN/UVLO and
V_CC UVLO are satisfied, an internal power-up sequence
soft-starts the error-amplifier reference, resulting in a
clean monotonic output-voltage soft-start independent of
the load current. The FB/V_OUT pin monitors the output
voltage through a resistor-divider. RESET transitions
to a high-impedance state 2ms after the output voltage
reaches 95% of regulation. The device selects either
PFM or forced-PWM mode depending on the state of the
MODE pin at power-up. By pulling the EN/UVLO pin to
low, the device enters the shutdown mode and consumes
only 2.2µA (typ) of standby current.
DC-DC Switching Regulator
The device uses an internally compensated, fixed-fre-
quency, current-mode control scheme (see the Block
Diagram). On the rising edge of an internal clock, the
high-side pMOSFET turns on. An internal error amplifier
compares the feedback voltage to a fixed internal refer-
ence voltage and generates an error voltage. The error
voltage is compared to a sum of the current-sense voltage
and a slope-compensation voltage by a PWM comparator
to set the on-time. During the on-time of the pMOSFET,
the inductor current ramps up. For the remainder of the
switching period (off-time), the pMOSFET is kept off and
the low-side nMOSFET turns on. During the off-time, the
inductor releases the stored energy as the inductor current
ramps down, providing current to the output. Under over-
load conditions, the cycle-by-cycle current-limit feature
limits the inductor peak current by turning off the high-side
pMOSFET and turning on the low-side nMOSFET.
Mode Selection (MODE)
The logic state of the MODE pin is latched after V_CC
and EN/UVLO voltages exceed respective UVLO rising
thresholds and all internal voltages are ready to allow
LXswitching. If the MODEpin is unconnected at power-
up, the part operates in PFM mode at light loads. If the
MODE pin is grounded at power-up, the part operates in
constant-frequency PWM mode at all loads. State chang-
es on the MODE pin are ignored during normal operation.
PWM Mode Operation
In PWM mode, the inductor current is allowed to go
negative. PWM operation is useful in frequency sensi-
tive applications and provides fixed switching frequency
at all loads. However, the PWM mode of operation gives
lower efficiency at light loads compared to PFM mode of
operation.
PFM Mode Operation
PFM mode operation disables negative inductor
current and additionally skips pulses at light loads for high
efficiency. In PFM mode, the inductor current is forced to
a fixed peak of 130mA every clock cycle until the output
rises to 102.3% of the nominal voltage. Once the output
reaches 102.3% of the nominal voltage, both high-side
and low-side FETs are turned off and the part enters
hibernate operation until the load discharges the output
to 101.1% of the nominal voltage. Most of the internal
blocks are turned off in hibernate operation to save
quiescent current. After the output falls below 101.1%
of the nominal voltage, the device comes out of hiber-
nate operation, turns on all internal blocks, and again
commences the process of delivering pulses of energy
to the output until it reaches 102.3% of the nomi-
nal output voltage. The device naturally exits PFM
mode when the load current exceeds 55mA
(typ). The advantage of the PFM mode is higher
efficiency at light loads because of lower quiescent
current drawn from supply.
Internal 5V Linear Regulator
An internal regulator provides a 5V nominal supply to
power the internal functions and to drive the power
MOSFETs. The output of the linear regulator (V_CC) should
be bypassed with a 1µF capacitor to GND. The V_CC regu-
lator dropout voltage is typically 150mV. An undervoltage-
lockout circuit that disables the regulator when V_CC falls
below 3.8V (typ). The 400mV V_CC UVLO hysteresis pre-
vents chattering on power-up and power-down.
Enable Input (EN/UVLO), Soft-Start
When EN/UVLO voltage is above 1.21V (typ), the device’s
internal error-amplifier reference voltage starts to ramp
up. The duration of the soft-start ramp is 4.1ms, allowing a
smooth increase of the output voltage. Driving EN/UVLO
low disables both power MOSFETs, as well as other inter-
nal circuitry, and reduces V_IN quiescent current to below
2.2µA. EN/UVLO can be used as an input-voltage UVLO
adjustment input. An external voltage-divider between V_IN
and EN/UVLO to GND adjusts the input voltage at which
the device turns on or turns off. If input UVLO program-
ming is not desired, connect EN/UVLO to V_IN (see the
Electrical Characteristics table for EN/UVLO rising and
falling threshold voltages).
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