DS26504 Datasheet, PDF (15/128 Pages) Maxim Integrated Products – T1/E1/J1/64KCC BITS Element

DS26504 T1/E1/J1/64KCC BITS Element
4.3 Receive Side
NAME
RCLK
RS_8K
400HZ
RSER
RLOF_CCE
RLOS
TYPE
O
O
O
O
O
O
FUNCTION
Receive Clock. Recovered 1.544MHz (T1), 2.048MHz (E1), 6312 kHz (G.703
Synchronization Interface), or 64kHz (Composite Clock) clock.
Payload Mode: When payload mode is enabled, this pin outputs a gapped clock
based on the internal RCLK. In T1 operation, the clock is gapped during the F-
bit position. In E1 mode, the clock is gapped during time slots 0 and 16.
Receive Sync/8kHz Clock
T1/E1 Mode: An extracted pulse, one RCLK wide, is output at this pin that
identifies either frame (IOCR1.5 = 0) or multiframe (IOCR1.5 = 1) boundaries.
If set to output frame boundaries, then through IOCR1.6, RS_8K can also be set
to output double-wide pulses on signaling frames in T1 mode.
64KCC Mode: This pin outputs the extracted 8kHz portion of the composite
clock signal.
6312kHz Mode: This pin is in a high-impedance state.
400Hz Clock Output
T1/E1 Mode: This pin is in a high-impedance state.
64KCC Mode: This pin outputs the 400Hz clock if enabled.
6312kHz Mode: This pin is in a high-impedance state.
Receive Serial Data
T1/E1 Mode: This is the received NRZ serial data updated on the rising edges of
RCLK.
64KCC Mode: This pin is in a high-impedance state.
6312kHz Mode: This pin is in a high-impedance state.
Receive Loss of Frame or Composite Clock Error. This output can be
configured to be a Loss-of-Transmit Clock indicator via IOCR.4 when operating
in T1 or E1 mode.
T1/E1 Mode: Set when the receive synchronizer is searching for frame
alignment (RLOF mode), or set when the signal at the TCLK pin has not
transitioned for approximately 15 periods of the scaled MCLK (LOTC mode).
64KCC Mode: Active high when errors are detected in the 8kHz clock or 400Hz
clock.
6312kHz Mode: This pin is in a high-impedance state.
Receive Loss of Signal
T1 Mode: High when 192 consecutive zeros detected.
E1 Mode: High when 255 consecutive zeros detected.
64KCC Mode: High when consecutive zeros detected for a minimum of 120ms
or the input signal falls below 0.3vp.
6312kHz Mode: High when consecutive zeros detected for a minimum of 60ms.
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