MAX9611 Datasheet, PDF (14/20 Pages) Maxim Integrated Products – High-Side, Current-Sense Amplifiers with 12-Bit ADC and Op Amp/Comparator

High-Side, Current-Sense Amplifiers with
12-Bit ADC and Op Amp/Comparator
Slave Address
A bus master initiates communication with a slave
device by issuing a START (S) condition followed by a
slave address. When idle, the MAX9611/MAX9612 con-
tinuously wait for a START condition followed by their
slave address. When the MAX9611/MAX9612 recognize
a slave address, it is ready to accept or send data. The
MAX9611/MAX9612 offer 16 different slave addresses
using two address inputs, A1 and A0. See Table 2 for
different slave address options. The least significant bit
(LSB) of the address byte (R/W) determines whether
the master is writing to or reading from the MAX9611/
MAX9612 (R/W = 0 selects a write condition, R/W = 1
selects a read condition). After receiving the address,
the MAX9611/MAX9612 (slave) issue an acknowledge
by pulling SDA low for one clock cycle.
I²C Write Operation
A write operation (Figure 1) begins with the bus master
issuing a START condition followed by seven address
bits and a write bit (R/W = 0). If the address byte is
successfully received, the MAX9611/MAX9612 (slave)
issue an acknowledge (A). The master then writes to
the slave and the sequence is terminated by a STOP (P)
condition for a single write operation.
For a burst write operation, more data bytes are sent after
the register address before the transaction is terminated.
Table 2. MAX9611/MAX9612 Address
Description
A1
0
0
0
0
1/3 x VCC
1/3 x VCC
1/3 x VCC
1/3 x VCC
2/3 x VCC
2/3 x VCC
2/3 x VCC
2/3 x VCC
VCC
VCC
VCC
VCC
A0
0
1/3 x VCC
2/3 x VCC
VCC
0
1/3 x VCC
2/3 x VCC
VCC
0
1/3 x VCC
2/3 x VCC
VCC
0
1/3 x VCC
2/3 x VCC
VCC
DEVICE WRITE
ADDRESS (hex)
0xE0
0xE2
0xE4
0xE6
0xE8
0xEA
0xEC
0xEE
0xF0
0xF2
0xF4
0xF6
0xF8
0xFA
0xFC
0xFE
DEVICE READ
ADDRESS (hex)
0xE1
0xE3
0xE5
0xE7
0xE9
0xEB
0xED
0xEF
0xF1
0xF3
0xF5
0xF7
0xF9
0xFB
0xFD
0xFF
I²C Read Operation
In an I²C read operation (Figure 2), the bus master
issues a write command first by initiating a START condi-
tion followed by seven address bits, a write bit (R/W = 0)
and the 8-bit register address. The master then issues
a Repeated START (Sr) condition, followed by seven
address bits, a read bit (R/W = 1). If the address byte
is successfully received, the MAX9611/MAX9612 (slave)
issue an acknowledge (A). The master then reads from
the slave. For continuous read, the master issues an
acknowledge bit (AM) after each received byte. The
master terminates the read operation by sending a not
acknowledge (NA) bit. The MAX9611/MAX9612 then
release the data line SDA allowing the master to gener-
ate a STOP condition.
SINGLE WRITE ACKNOWLEDGE FROM
MAX9611/MAX9612
S
SLAVE ADDRESS 0 A
REGISTER ADDRESS
R/W
A
DATA
AP
BURST WRITE
S
STOP
ACKNOWLEDGE FROM
MAX9611/MAX9612
SLAVE ADDRESS 0 A
REGISTER ADDRESS
R/W
A
DATA 1
A
DATA 2
A
DATA 3
A
DATA N
AP
STOP
Figure 1. I²C Write Operation
SINGLE READ ACKNOWLEDGE FROM
MAX9611/MAX9612
S SLAVE ADDRESS 0 A
REGISTER ADDRESS
A Sr
R/W
SLAVE ADDRESS 1 A
DATA
AM P
BURST READ
R/W
ACKNOWLEDGE FROM
MAX9611/MAX9612
S SLAVE ADDRESS
0A
ACKNOWLEDGE FROM
FROM MASTER
REGISTER ADDRESS
A Sr
REPEAT
START
AM
R/W
SLAVE ADDRESS 1 A
R/W
DATA
AM
DATA
DATA N
NA P
NO READ-ACKNOWLEDGE
FROM MASTER
Figure 2. I²C Read Operation
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