MAX5122 Datasheet, PDF (14/20 Pages) Maxim Integrated Products – +5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/°C Internal Reference

+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
Table 3. Detailed SSPCON Register Contents
CONTROL BIT
WCOL
SSPOV
BIT7
BIT6
SSPEN
BIT5
CKP
SSPM3
SSPM2
SSPM1
SSPM0
X = Don’t care
BIT4
BIT3
BIT2
BIT1
BIT0
MAX5122/MAX5123
SETTINGS
X
X
1
0
0
0
0
1
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER
(SSPCON)
Write Collision Detection Bit
Receive Overflow Detect Bit
Synchronous Serial Port Enable Bit.
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO and SCI as serial-
port pins.
Clock Polarity Select Bit. CKP = 0 for SPI master-mode selection.
Synchronous Serial Port Mode Select Bit. Sets SPI master mode
and selects f_CLK = f_OSC / 16
Table 4. Detailed SSPSTAT Register Contents
CONTROL BIT
SMP
BIT7
CKE
D/A
P
S
R/W
UA
BF
X = Don’t care
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
MAX5130/MAX5131
SETTINGS
0
1
X
X
X
X
X
X
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER
(SSPSTAT)
SPI Data Input Sample Phase. Input data is sampled at the mid-
dle of the data output time.
SPI Clock Edge Select Bit. Data will be transmitted on the rising
edge of the serial clock.
Data Address Bit
Stop Bit
Start Bit
Read/Write Bit Information
Update Address
Buffer Full Status Bit
Serial Data Output
The contents of the internal shift-register are output
serially on DOUT which allows for daisy-chaining of
multiple devices (see Applications Information) as well
as data readback. The MAX5122/MAX5123 may be
programmed to shift data out of DOUT on the serial
clock’s rising edge (Mode 1) or on the falling edge
(Mode 0). The latter is the default during power-up and
provides a lag of 16 clock cycles, maintaining SPI,
QSPI, MICROWIRE, and PIC16/PIC17 compatibility. In
Mode 1, the output data lags DIN by 15.5 clock cycles.
During power-down, DOUT retains its last digital state
prior to shutdown.
User-Programmable Output (UPO)
The UPO feature allows an external device to be con-
trolled through the serial-interface setup (Table 1) there-
by reducing the number of microcontroller I/O ports
required. During power-down, this output will retain the
last digital state before shutdown. With CLR pulled low,
UPO will reset to the default state after wake-up.
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