MAX15020 Datasheet, PDF (14/19 Pages) Maxim Integrated Products – 2A, 40V Step-Down DC-DC Converter with Dynamic Output-Voltage Programming

2A, 40V Step-Down DC-DC Converter with
Dynamic Output-Voltage Programming
Compensation Design
The MAX15020 uses a voltage-mode control scheme
that regulates the output voltage by comparing the
error-amplifier output (COMP) with an internal ramp to
produce the required duty cycle. The output lowpass
LC filter creates a double pole at the resonant frequen-
cy, which has a gain drop of -40dB/decade. The error
amplifier must compensate for this gain drop and
phase shift to achieve a stable closed-loop system.
The basic regulator loop consists of a power modulator,
an output feedback divider, and a voltage error amplifi-
er. The power modulator has a DC gain set by V_IN /
V_RAMP, with a double pole and a single zero set by the
output inductance (L), the output capacitance (C_OUT)
(C6 in the Figure 2) and its ESR. The power modulator
incorporates a voltage feed-forward feature, which auto-
matically adjusts for variations in the input voltage
resulting in a DC gain of 9. The following equations
define the power modulator:
G_MOD(DC)
=
V_IN
V_RAMP
=9
f_LC = _2π
1
L×C
f_ESR
=
2π
×
1
C_OUT
×
ESR
The switching frequency is internally set at 300kHz or
500kHz, or can vary from 100kHz to 500kHz when driven
with an external SYNC signal. The crossover frequency
(f_C), which is the frequency when the closed-loop gain is
equal to unity, should be set as f_SW / 2π or lower.
The error amplifier must provide a gain and phase
bump to compensate for the rapid gain and phase loss
from the LC double pole. This is accomplished by utiliz-
ing a Type 3 compensator that introduces two zeros
and three poles into the control loop. The error amplifier
has a low-frequency pole (f_P1) near the origin.
In reference to Figures 3 and 4, the two zeros are at:
f_Z1
=
2π
1
× R9 ×
C12
and
f_Z2
=
2π
×
(R6
1
+ R7)
× C11
And the higher frequency poles are at:
f_P2
=
2π
×
1
R6
× C11
and
f_P3
=
2π
× R9
×
1
⎛ C12
⎝⎜ C12
× C13 ⎞
+ C13⎠⎟
Compensation when f_C < f_ESR
Figure 3 shows the error-amplifier feedback as well as
its gain response for circuits that use low-ESR output
capacitors (ceramic). In this case f_ZESR occurs after f_C.
f_Z1 is set to 0.8 x f_LC(MOD) and f_Z2 is set to f_LC to com-
pensate for the gain and phase loss due to the double
pole. Choose the inductor (L) and output capacitor
(C_OUT) as described in the Inductor Selection and
Output Capacitor Selection sections.
Choose a value for the feedback resistor R6 in Figure 3
(values between 1kΩ and 10kΩ are adequate).
C12 is then calculated as:
C12 =
1
2π × 0.8 × f_LC × R9
f_C occurs between f_Z2 and f_P2. The error-amplifier gain
(GEA) at f_C is due primarily to C11 and R9.
Therefore, GEA(f_C) = 2π x f_C x C11 x R9 and the modu-
lator gain at f_C is:
G_MOD(fC)
=
(2π)²
G_MOD(DC)
× L × C_OUT
×
f_C2
Since G_EA(fC) x G_MOD(fC) = 1, C11 is calculated by:
C11 = ^{fC × L × COUT × 2π}
R9 × G_MOD(DC)
f_P2 is set at 1/2 the switching frequency (f_SW). R6 is
then calculated by:
R6 =
1
2π × C11× 0.5 × f_SW
Since R7 >> R6, R7 + R6 can be approximated as R7.
R7 is then calculated as:
R7 =
1
2π × f_LC × C11
f_P3 is set at 5 x f_C. Therefore, C13 is calculated as:
C13 =
C12
2π × C12 × R9 × f_P3 − 1
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