MAX13442E Datasheet, PDF (14/18 Pages) Maxim Integrated Products – ±15kV ESD-Protected, ±80V Fault-Protected, Fail-Safe RS-485/J1708 Transceivers

±15kV ESD-Protected, ±80V Fault-Protected,
Fail-Safe RS-485/J1708 Transceivers
Hot-Swap Capability
Hot-Swap Inputs
Inserting circuit boards into a hot, or powered, back-
plane may cause voltage transients on DE, RE, and
receiver inputs A and B that can lead to data errors. For
example, upon initial circuit board insertion, the proces-
sor undergoes a power-up sequence. During this period,
the high-impedance state of the output drivers makes
them unable to drive the MAX13442E/MAX13443E/
MAX13444E enable inputs to a defined logic level.
Meanwhile, leakage currents of up to 10µA from the
high-impedance output, or capacitively coupled noise
from V_CC or GND, could cause an input to drift to an
incorrect logic state. To prevent such a condition from
occurring, the MAX13442E/MAX13443E/MAX13444E
feature hot-swap input circuitry on DE, and RE to guard
against unwanted driver activation during hot-swap sit-
uations. The MAX13444E has hot-swap input circuitry
only on RE. When V_CC rises, an internal pulldown (or
pullup for RE) circuit holds DE low for at least 10µs, and
until the current into DE exceeds 200µA. After the initial
power-up sequence, the pulldown circuit becomes
transparent, resetting the hot-swap tolerable input.
Hot-Swap Input Circuitry
At the driver-enable input (DE), there are two NMOS
devices, M1 and M2 (Figure 10). When V_CC ramps from
zero, an internal 15µs timer turns on M2 and sets the
SR latch, which also turns on M1. Transistors M2, a
2mA current sink, and M1, a 100µA current sink, pull
DE to GND through a 5.6kΩ resistor. M2 pulls DE to the
disabled state against an external parasitic capaci-
tance up to 100pF that may drive DE high. After 15µs,
the timer deactivates M2 while M1 remains on, holding
DE low against tri-state leakage currents that may drive
DE high. M1 remains on until an external current source
overcomes the required input current. At this time, the
SR latch resets M1 and turns off. When M1 turns off, DE
reverts to a standard, high-impedance CMOS input.
Whenever V_CC drops below 1V, the input is reset.
A complementary circuit for RE uses two PMOS
devices to pull RE to V_CC.
1MR^C9
1.R5^Dk9
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
SOURCE
Cs
100pF
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
V_CC
TIMER
15μs
TIMER
Figure 9a. Human Body ESD Test Model
I_P 100%
90%
Ir
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
AMPERES
36.8%
10%
0
0 _tRL
TIME
t_DL
CURRENT WAVEFORM
Figure 9b. Human Body Model Current Waveform
DE
(HOT SWAP)
5.6kΩ
100μA ^2mA
M1
M2
Figure 10. Simplified Structure of the Driver Enable Pin (DE)
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