MAX1298 Datasheet, PDF (14/20 Pages) Maxim Integrated Products – 12-Bit Serial-Output Temperature Sensors with 5-Channel ADC

12-Bit Serial-Output Temperature Sensors
with 5-Channel ADC
CS
SCLK
DIN
DOUT
t_CSO
t_CSS
t_CH
t_DS
X
t_DH
VALID
X
t_DV
t_CL
VALID
t_DO
t_CS
t_CSH
t_CS1
VALID
X
t_TR
Figure 4. Detailed Serial Interface Timing
OUTPUT CODE
011111111111
011111111110
000000000010
000000000001
000000000000
111111111111
111111111110
111111111101
+FS = + _2VREF
-FS = - _2VREF
1LSB
=
2V_REF
2048
100000000010
100000000001
- _FS + _1LSB
0
IN+ ^- IN ^- (LSB)
Figure 5. Bipolar Transfer Function
+ _FS - _1LSB
Input Data Format
Input data (configuration and conversion bytes) are
clocked into the MAX1298/MAX1299 at DIN on the ris-
ing edge of SCLK when CS is low. The start bit (MSB)
of an input data byte is the first logic 1 bit that arrives:
After CS falls,
OR
after receipt of a complete configuration byte with no
conversion in progress,
OR
after 16 bits have been clocked onto DOUT following a
conversion.
Output Data Format
Output data from the MAX1298/MAX1299 are clocked
onto DOUT on the falling edge of SCLK in the form of two
8-bit words, MSB first (Table 1). For temperature conver-
sions, the output is 12-bit binary (D10–S0) padded with 2
leading extraneous bits and two trailing zeros. For volt-
age conversions, the output is 12-bit two’s-complement
binary (D11–D0) with 1 sub-bit and two trailing zeros.
Figure 5 shows the bipolar transfer function.
Performing a Conversion
On power-up, the MAX1298/MAX1299 defaults to shut-
down mode. Start a conversion by transferring a configu-
ration byte and a conversion byte into DIN with the
control formats shown in Tables 2 and 3, respectively.
(See Power Modes for related discussion.)
SSTRB goes low on the falling edge of the last bit of the
conversion byte, and it returns high when the conversion
is complete. For best noise performance, SCLK should
remain low while SSTRB is low. Typical conversion times
are 2.2ms for temperature measurements and 1.1ms for
voltage measurements. The MSB of the 2 output bytes is
present at DOUT starting at the rising edge of SSTRB.
Successive SCLK falling edges shift the two 8-bit data
bytes out from an internal register. Additional (>16)
SCLK edges will result in zeros on DOUT.
SSTRB does not go into a high-impedance state when
CS goes high. Pulling CS high prevents data from
being clocked in or out, but it does not adversely affect
a conversion in progress. Figure 6 shows SSTRB timing
details.
Subsequent conversions with the same reference mode
do not require a configuration byte.
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