DS33R11 Datasheet, PDF (132/338 Pages) Maxim Integrated Products – Ethernet Mapper with Integrated T1/E1/J1 Transceiver

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
7
Name
-
Default
-
GL.RTCAL
Global Receive and Transmit Serial Port Clock Activity Latched Status
04h
6
5
4
3
2
1
0
-
-
RLCALS1
-
-
-
TLCALS1
-
-
-
-
-
-
-
Bit 4: Receive Serial Interface Clock Activity Latched Status 1 (RLCALS1) This bit is set to 1 if the receive
clock for Serial Interface 1 has activity. This bit is cleared upon read.
Bit 0: Transmit Serial Interface Clock Activity Latched Status 1 (TSCALS1) This bit is set to 1 if the transmit
clock for Serial Interface 1 has activity. This bit is cleared upon read.
Register Name:
Register Description:
Register Address:
Bit #
7
Name
-
Default
-
GL.SRCALS
Global SDRAM Reference Clock Activity Latched Status
05h
6
5
4
3
2
1
0
-
-
-
-
-
REFCLKS SYSCLS
-
-
-
-
-
-
-
Bit 1: Reference Clock Activity Latched Status (REFCLKS) This bit is set to 1 if REF_CLK has activity. This bit
is cleared upon read.
Bit 0: System Clock Input Latched Status (SYSCLS) This bit is set to 1 if SYSCLKI has activity. This bit is
cleared upon read.
Register Name:
Register Description:
Register Address:
Bit #
7
6
Name
-
-
Default
0
0
GL.LIE
Global Serial Interface Interrupt Enable
06h
5
4
3
2
-
LIN1TIE
-
-
0
0
0
0
1
0
-
LIN1RIE
0
0
Bit 4: Serial Interface 1 TX Interrupt Enable (LINE1TIE) Setting this bit to 1 enables an interrupt on LIN1TIS
Bit 0: Serial Interface 1 RX Interrupt Enable (LINE1RIE) Setting this bit to 1 enables an interrupt on LIN1RIS
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