MAX1446 Datasheet, PDF (13/16 Pages) Maxim Integrated Products – 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference

10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
the input. Although a 1:1 transformer is shown, a step-
up transformer may be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, may also improve the over-
all distortion.
In general, the MAX1446 provides better SFDR and
THD with fully differential input signals than single-
ended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower since both inputs (IN+, IN-) are balanced, and
each of the inputs only requires half the signal swing
compared to single-ended mode.
Single-Ended AC-Coupled
Input Signal
Figure 9 shows an AC-coupled, single-ended applica-
tion. The MAX4108 op amp provides high speed, high
bandwidth, low noise, and low distortion to maintain the
integrity of the input signal.
Grounding, Bypassing,
__________________and Board Layout
The MAX1446 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side as
the ADC, using surface-mount devices for minimum
inductance. Bypass V_DD, REFP, REFN, and COM with
two parallel 0.1µF ceramic capacitors and a 2.2µF
bipolar capacitor to GND. Follow the same rules to
bypass the digital supply (OV_DD) to OGND. Multilayer
boards with separated ground and power planes pro-
duce the highest level of signal integrity. Consider
using a split ground plane arranged to match the physi-
OE
OUTPUT
DATA D9–D0
t_ENABLE
HIGH-Z
Figure 5. Output Enable Timing
VALID DATA
t_DISABLE
HIGH-Z
ANALOG INPUT
5.5 CLOCK-CYCLE LATENCY
N
N+1
N+2
N+3
N+4
N+5
N+6
CLOCK INPUT
DATA OUTPUT
t_DO
t_CH
t_CL
N-6
N-5
N-4
N-3
N-2
N-1
N
N+1
Figure 6. System and Output Timing Diagram
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