MAX144 Datasheet, PDF (13/16 Pages) Maxim Integrated Products – +2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin μMAX

+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
Table 3. Detailed SSPSTAT Register Contents
CONTROL BIT
SMP
BIT7
CKE
D/A
P
S
R/W
UA
BF
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
X = Don’t care
MAX144/MAX145
SETTINGS
SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT)
0
SPI Data Input Sample Phase. Input data is sampled at the middle of the data output
time.
1
SPI Clock Edge Select Bit. Data will be transmitted on the rising edge of the serial clock.
X
Data Address Bit
X
Stop Bit
X
Start Bit
X
Read/Write Bit Information
X
Update Address
X
Buffer Full Status Bit
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards
(PCBs). Wire-wrap configurations are not recommend-
ed, since the layout should ensure proper separation of
analog and digital traces. Run analog and digital lines
anti-parallel to each other, and don’t lay out digital sig-
nal paths underneath the ADC package. Use separate
analog and digital PCB ground sections with only one
star-point (Figure 11) connecting the two ground systems
V_DD
V_DD
SCLK
SCK
DOUT
SDI
CS/SHDN
I/O
(analog and digital). For lowest-noise operation, ensure
the ground return to the star ground’s power supply is
low impedance and as short as possible. Route digital
signals far away from sensitive analog and reference
inputs.
High-frequency noise in the power supply V_DD could
influence the proper operation of the ADC’s fast com-
parator. Bypass V_DD to the star ground with a network
of two parallel capacitors (0.1µF and 1µF) located as
close as possible to the power supply pin of MAX144/
MAX145. Minimize capacitor lead length for best sup-
ply-noise rejection and add an attenuation resistor
(10Ω) if the power supply is extremely noisy.
MAX144
MAX145
PIC16/17
GND
GND
Figure 10a. SPI Interface Connection for a PIC16/PIC17
Controller
SCLK
CS/SHDN
1ST BYTE READ
1 2345678
2ND BYTE READ
9 10 11 12 13 14 15 16
DOUT*
CHID D11 D10 D9 D8
SAMPLING INSTANT MSB
*WHEN CS/SHDN IS HIGH, DOUT = HIGH-Z
D7
D6 D5 D4 D3 D2 D1 D0
LSB
Figure 10b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3–SSPM0 = 0001)
HIGH-Z
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