MAX1193 Datasheet, PDF (13/26 Pages) Maxim Integrated Products – Ultra-Low-Power, 45Msps, Dual 8-Bit ADC

Ultra-Low-Power, 45Msps, Dual 8-Bit ADC
Pin Description (continued)
PIN
NAME
FUNCTION
23
PD0
Power-Down Digital Input 0. See Table 3.
24
REFIN Reference Input. Internally pulled up to V_DD.
25
COM
Common-Mode Voltage I/O. Bypass COM to GND with a 0.33µF capacitor.
26
REFN
Negative Reference I/O. Conversion range is ±(V_REFP - V_REFN). Bypass REFN to GND with a 0.33µF
capacitor.
27
REFP
Positive Reference I/O. Conversion range is ±(V_REFP - V_REFN). Bypass REFP to GND with a 0.33µF
capacitor.
—
EP
Exposed Paddle. Internally connected to pin 3. Externally connect EP to GND.
+
T/H
∑
x2
-
FLASH
ADC
DAC
INA+
T/H
INA-
1.5 BITS
STAGE 1
STAGE 2
STAGE 7
DIGITAL ERROR CORRECTION
D0–D7
Figure 1. Pipeline Architecture—Stage Blocks
Detailed Description
The MAX1193 uses a seven-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half-clock cycle.
Including the delay through the output latch, the total
clock-cycle latency is 5 clock cycles for channel A and
5.5 clock cycles for channel B.
At each stage, flash ADCs convert the held input volt-
ages into a digital code. The following digital-to-analog
converter (DAC) converts the digitized result back into
an analog voltage, which is then subtracted from the
originally held input signal. The resulting error signal is
then multiplied by two, and the product is passed along
to the next pipeline stage where the process is repeated
until the signal has been processed by all stages. Digital
error correction compensates for ADC comparator off-
sets in each pipeline stage and ensures no missing
codes. Figure 2 shows the MAX1193 functional diagram.
INA+
INA-
REFIN
REFP
COM
REFN
INB+
INB-
PIPELINE
T/H
ADC
/ DEC
A
V_DD
GND
MAX1193 _POWER
PD0
CONTROL
PD1
OV_DD
REFERENCE
SYSTEM AND
BIAS
CIRCUITS
MULTIPLEXER
OUTPUT
DRIVERS
D0–D7
A/B
OGND
PIPELINE
T/H
ADC
/ DEC
B
TIMING
CLK
Figure 2. MAX1193 Functional Diagram
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